Symbol
FCE[7:0]#
PWD0#/WP#
PWD1#/SE#
FRY/FBY#
MX9691L
No.
43-44,
46-47
49-52
32
64
13
Type
O
(CMOS)
O
(CMOS)
O
(CMOS)
I
(CMOS)
Description
Flash memory chip enable 7-0 :
In linear mode, These signals are decoded from port 601Dh
bit 7-5 when flash memory read or port 601Fh bit 7-5 when
flash memory write.
Decoding combination :
bit7 bit6 bit5 FCE[7:0]#
0 0 0 11111110
0 0 1 11111011
0 1 0 11101111
0 1 1 10111111
1 0 0 11111101
1 0 1 11110111
1 1 0 11011111
1 1 1 01111111
In series mode, These are decoded from port 601Dh bit 7-5
only when port 601Eh bit 2 is set.
In linear mode, this signal is used as deep power-down
control of flash memory chips of bank0. PWD0# is active
low and also locks out erase or program operation providing
data protection during power transitions. Power down pin
PWD0# will be active if FA23=1.
In series mode, this signal is used to protect the device from
inadvertent programming or erasing. WP# is active low.
In linear mode, this signal is used as deep power-down
control of flash memory chips of bank1. PWD1# is active
low and also locks out erase or program operation providing
data protection during power transitions. Power down pin
PWD0# will be active if FA23=0. In series mode,this signal
is used to spare area control. SE# is active low.
Flash memory Ready/busy input:
This signal indicate the state of erase or program operation
in flash memory chips.This pin includes an internal pull-up
resistor.
P/N:PM0546
REV. 1.1, JUL. 02, 1999
9