CDP1877 View Datasheet(PDF) - Intersil
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CDP1877 Datasheet PDF : 10 Pages
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CDP1877, CDP1877C
Example 2 - Multi-PIC Application
Figure 3 shows all the connections required between CPU
and PIC’s to handle sixteen levels of interrupt control.
MA7
MA6
MA5
CPU MA1
CDP1802 MA0
MWR
MRD
TPA
TPB
INT
BUS
CS/AX
CASC
CS/AY
CS PIC 1
CS CDP1877
IR7
MWR
IR6
MRD
IR5
TPA
IR4
TPB
IR3
INT
IR2
IR1
BUS
IR0
+V
HIGHEST
PRIORITY
INTERRUPT
CS/AX
CASC
CS/AY
CS
PIC 2 IR7
CS CDP1877 IR6
MWR
IR5
MRD
IR4
TPA
IR3
TPB
IR2
IR1
INT
IR0
BUS
LOWEST
PRIORITY
INTERRUPT
FIGURE 3. PICs AND CPU CONNECTION DIAGRAM
Register Address Assignments
The low-byte register address for any WRITE or READ
operation is the same as shown in Table 1.
The High-Byte register differs for each PIC because of the
linear addressing technique shown in the example:
PIC 1 = 111XXX01 (E1H for X = 0)
PIC 2 = 111XXX10 (E2H for X = 0)
The R(1) vector address is unchanged. This address will
select both PICs simultaneously (R(1). 1 = 111XXX00 =
E0H). Internal CDP1877 logic controls which PIC will
respond when an interrupt request is serviced.
Additional PIC Application Comments
The interval select options provide significant flexibility for
interrupt routine memory allocations:
• The 2-byte interval allows one to dedicate a full page to
interrupt servicing, with variable space between routines,
by specifying indirect vectoring with 2-byte short branch
instructions on the current page.
• The 4-byte interval allows for a 3-byte long branch to any
location in memory where the interrupt service routine is
located. The branch can be preceded by a Save
Instruction to save previous contents of X and P on the
stack.
• The 8-byte and 16-byte intervals allow enough space to
perform a service routine without indirect vectoring. The
amount of interval memory can be increased even further
if all 8 INTERRUPTS are not required. Thus a 4-level inter-
rupt system could use alternate IR Inputs, and expand the
interval to 16 and 32 bytes, respectively.
• The 4 Chip Selects allow one to conserve total allotted
memory space to the PIC. For one chip, a total of 4
address lines could be used to select the device, mapping
it into as little as 4-K of memory space. Note that this
selection technique is the only one that allows the PIC to
work properly in the system: I/O mapping cannot be used
because the PIC must work within the CDP1800 interrupt
structure to define the vector address. Decoded signals
also will not work because the chip selects must be valid
on the trailing edge of TPA.
4-89
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