CDP1877 View Datasheet(PDF) - Intersil
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Description
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CDP1877 Datasheet PDF : 10 Pages
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CDP1877, CDP1877C
Functional Definitions for CDP1877 and CDP1877C Terminals
TERMINAL
VDD - VSS
BUS0 - BUS7
IR0 - IR7
INTERRUPT
MRD, MWR
TPA, TPB
CS, CS
CS/AX, CS/AY
CASCADE
USAGE
Power
Data Bus - Communicates Information to and from CPU
Interrupt Request Lines
Interrupt to CPU
Read/Write Controls from CPU
Timing Pulses from CPU
Chip Selects, Enable Chip if Valid during TPA
Used as a Chip Select during TPA and as a Register Address During Read/Write Operations
Used for Cascading Several PIC Units. The INTERRUPT Output from a Higher
Priority PIC can be Tied to this Input, or the Input can be Tied to VDD if Cascading is Not Used.
PIC Programming Model
TYPE
Bidirectional
Input
Output
Input
Input
Input
Input
Input
INTERNAL REGISTERS
The PIC has three write-only programmable registers and
two read-only registers.
Page Register
This write only register contains the high order vector
address the device will issue in response to an interrupt
request. This high-order address will be the same for any of
the 8 possible interrupt requests; thus, interrupt vectoring dif-
fers only in location within a specified page.
BUS 7
A15
A14
PAGE REGISTER BITS
A13
A12
A11
A10
BUS 0
WRITE ONLY
A9
A8
Control Register
The upper nibble of this write-only register contains the low
order vector address the device will issue in response to an
interrupt request. The lower nibble is used for a master
interrupt reset, master mask reset and for interval select.
BUS 7
B7
B6
CONTROL REGISTER BITS
B5
B4
B3
B2
BUS 0
WRITE ONLY
B1
B0
INTERVAL SELECT DETERMINES
NUMBER OF BYTES ALLOCATED TO
EACH INTERRUPT SERVICE ROUTINE
BIT 1
BIT 0
INTERVAL
0
0
2
0
1
4
1
0
8
1
1
16
MASTER MASK RESET
0 RESETS ALL MASK REGISTER BITS
1 NO CHANGE
MASTER INTERRUPT RESET
0 RESETS ALL INTERRUPT LATCHES, CLEARS ANY
PENDING INTERRUPTS
1 NO CHANGE
SETS UPPER BITS OF THE LOW ORDER VECTOR ADDRESS AS A
FUNCTION OF THE INTERVAL SELECT
4-85
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