[NON-DISCLOSURE AGREEMENT REQUIRED]

Overview
EPF011A/EPF011C/EPF011D is a low cost high performance Micro Controller. The chip integrates 80515 core, 64KB embedded Flash, 256 + 2KB RAM, Timer, Watchdog Timer, Serial Port, 8-bit PWM, SPI, IIC Slave, IIC Master, 10-bit ADC, USB 1.1, Remote Decoder, Keyboard Interrupt and GPIO in a single chip.

FEATUREs
• On-chip 80515 core with 64K bytes Flash, 256 bytes Direct RAM
   and 2K bytes on-chip auxiliary RAM
• Fast CPU rate (24Mhz). 41.6 ns for shortest instruction
• Programmable CPU clocks from 24 Mhz to 500 Khz
• Programmable crystal start-up cycles from 0 to 4096 cycles
• Supports Idle mode and Stop mode for power saving.
• Supports crystal/CPU wake-up from Stop mode
• Supports In Circuit Flash programming (ICP)
• Supports 2 external interrupts
• Supports keyboard interrupt on 4 GPIO pins.
• On-chip 4 Timers supporting Timer, Pulse Output,
   Event Counter and Pulse Width Measurement modes
• On-chip 15-bit programmable Watchdog Timer
• On-chip Serial Port which supports Synchronous mode
   and 8/9-bit UART modes
• On-chip Serial Peripheral Interface (SPI)
• On-chip 4 channels of 8-bit PWM with programmable repetition rate
• On-chip 4 channels of 10-bit ADC
• On-chip IIC Master and Slave ports with configurable pin outs
• On-chip USB 1.1 which supports end-pint 0, 1 and 2
• On-chip Consumer Infra-Red Remote Receiver (CIR)
   which supports NEC and Phillips RC-5 protocols
• EPF011A supports 9 General Purpose I/O Ports (total 44 I/O pins).
   Among them, 6 ports are open-drain programmable and
   2 ports has 20 mA sink capability. All I/O ports are 5V tolerant.
• EPF011D supports 9 General Purpose I/O Ports (total 31 I/O pins).
   Among them, 6 ports are open-drain programmable
   and 2 ports has 20 mA sink capability. All I/O ports are 5V tolerant.
• EPF011C supports 7 General Purpose I/O Ports (total 14 I/O pins).
   Among them, 4 ports are open-drain programmable and 1 ports has 20 mA
   sink capability. All I/O ports are 5V tolerant.
• Timer, SPI and ADC pins can be additional GPIO
   if the associated function is not enabled
• On-chip Low Voltage Inhibit (LVI) circuit which provides
   reliable power up reset and prevent accidental data loss in Flash
• Single 24 MHz crystal required
• Single 3.3V CMOS design
• 64-pin LQFP package (Pb-Free) for EPF011A,
   48-pin LQFP package (Pb-Free) for EPF011D,
   24-Pin SSOP (Pb-Free) for EPF011C