CS5106 View Datasheet(PDF) - Cherry semiconductor
Part Name
Description
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CS5106 Datasheet PDF : 12 Pages
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Block Diagram
OUVDELAY
OAOUT
OAM
VSS
VCC
V5REF
RAMP1
VFB1
GATE1
Gnd
ILIM1
VCC
Aux. Error Amp
5V
G1
A1
1.2V +
V
D1
45k
5k
V
-
C+2
Output
Undervoltage
Timer
RSFF
RQ
F1
S
Set Dominant
VREFOK
G18
Fault Latch
RSFF
C4
RUN 1 Q R
G4
G3
ENABLE
Comparator
P1
100k
RUN1
F2
G5
S
1.4V
Reset
C7
V TPERIOD Dominant
A2
G6
RUN 2
VSS
VSS Restart
Comparator Under Voltage
Comparator
V 1.4V
Over Voltage
Comparator
CLK1 SYNCIN
Sync Detection
+
START
-STOP
ENABLE VREF
VREF=5V
VREFOK Comparator
-
4.5 +C9
OSC
CLK2SYNCOUT
IFSET IDSET
G7
G8
FREQ
TOO HIGH
FREQ
TOO LOW
V 7.4/6.8V
V
VREFOK
+ 1.5V A2
V
C1
1.4V
-
V
C3+
-
C5+
5V V
-
C8+
TFF
Q
T1
0.13V +
+ 0.13V
DRIVER G9
2R
R
RUN1
Aux.PWM
Comparator -
C10+
RSFF
QR
F4
S
Reset
Dominant
G10
-
C12+
Aux. Current
Limit Comparator
G14
CLOCK
Skip2B Skip Two
Clock Pulses
SET
1.2V
V
C16 1.4V
Aux. 2nd Current
Threshold Comparator
V
Main PWM
- Comparator
+C11
2R
R
RUN2
G11
-
+C13
Main Current
Limit Comparator
CLOCK
Skip Two
Skip2B
Clock Pulses
SET
RSFF
RQ
F3
SQ
Reset
Dominant
G15
-
+C17
Main 2nd Current
Threshold Comparator
G13
DELAY
C14
RUN2
G17
DELAY
-
C15+
G12
DRIVER
G16
DRIVER
1.7V +
V
PROGRAM
ENABLE
UVSD
OVSD
SYNCIN
SYNCOUT
DYLSET
FADJ
RAMP2
VFB2
GATE2
GATE2B
ILIM2
Theory of Application
Theory of Operation
Powering the IC
The IC has one supply, VCC, and one Ground lead. If VSS is
used for a bootstrapped supply the diode between VSS and
VCC is forward biased, and the IC will derive its power
from VSS. The internal logic monitors the supply voltage,
VCC. During abnormal operating conditions, all GATE
drivers are held in a low state. The CS5106 requires 1.5mA
nominal of startup current.
Startup
Assume the part is enabled and there are no over voltage
or under voltage faults present. Also, assume that all auxil-
iary and main regulated output voltages start at 0V. An
8V, Zener referenced supply is typically applied to VCC.
When VCC exceeds 7.5V, the 5V reference is enabled and
the OSC begins switching. If the V5REF lead is not exces-
sively loaded such that V5REF < 4.5V nominal, ÔVREFOKÕ
goes ÔhighÕ and ÔRUN1Õ will go ÔhighÕ, releasing GATE1
from its low state. After GATE1 is released, it begins
switching according to conditions set by the auxiliary con-
trol loop and the auxiliary supply, VSS begins to rise.
When VSS > VCC + V(D1), P1 turns on and ÔRUN2Õ goes
ÔhighÕ, releasing GATE2 and GATE2B from their low state.
GATE2 and GATE2B begin switching according to condi-
tions set by the main control loop and the main regulated
output begins to rise. See startup waveforms in Figure 1.
Soft Start
Soft start for the auxiliary power supply is accomplished
by placing a capacitor between OAOUT and Ground. The
error amplifier has 200µA of nominal of source current and
is ideal for setting up a Soft Start condition for the auxiliary
regulator. Care should be taken to make sure that the soft
start timing requirements are not in conflict with any tran-
sient load requirements for the auxiliary supply as large
capacitors on OAOUT will slow down the loop response.
Also, the Soft start capacitor must be chosen such that dur-
ing start or restart, both outputs will come into regulation
before the OUVDELAY timer trips. Soft Start for the main
supply is accomplished by charging soft start capacitor C6
through D5 and R7 at start up. After the main supply has
come into regulation C6 continues to charge and is discon-
nected from the feedback loop by D8.
8
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