ADN2816XCPZ View Datasheet(PDF) - Analog Devices

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ADN2816XCPZ

Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC

Analog Devices 

Preliminary Technical Data

Transmission Lines

Use of 50 Ω transmission lines is required for all high frequency

input and output signals to minimize reflections: PIN, NIN,

CLKOUTP, CLKOUTN, DATAOUTP, DATAOUTN (also

REFCLKP, REFCLKN, if a high frequency reference clock is

used, such as 155 MHz). It is also necessary for the PIN/NIN

input traces to be matched in length, and the CLKOUTP/N and

DATAOUTP/N output traces to be matched in length to avoid

skew between the differential traces.

The high speed inputs, PIN and NIN, are internally terminated

with 50 Ω to an internal reference voltage (see Figure 19).

A 0.1 µF is recommended between VREF, Pin 3, and GND to

provide an ac ground for the inputs.

As with any high speed mixed-signal design, take care to keep

all high speed digital traces away from sensitive analog nodes.

VCC

ADN2816

50Ω CIN PIN

TIA

50Ω CIN NIN

0.1µF

50Ω 50Ω

VREF

3kΩ

2.5V

Figure 19. ADN2816 AC-Coupled Input Configuration

Soldering Guidelines for Chip Scale Package

The lands on the 32 LFCSP are rectangular. The printed circuit

board pad for these should be 0.1 mm longer than the package

land length and 0.05 mm wider than the package land width.

The land should be centered on the pad. This ensures that the

solder joint size is maximized. The bottom of the chip scale

package has a central exposed pad. The pad on the printed

circuit board should be at least as large as this exposed pad. The

user must connect the exposed pad to VEE using plugged vias

so that solder does not leak through the vias during reflow. This

ensures a solid connection from the exposed pad to VEE.

Choosing AC Coupling Capacitors

AC coupling capacitors at the input (PIN, NIN) and output

(DATAOUTP, DATAOUTN) of the ADN2816 must be chosen

such that the device works properly over the full range of data

ADN2816

rates used in the application. When choosing the capacitors, the

time constant formed with the two 50 Ω resistors in the signal

path must be considered. When a large number of consecutive

identical digits (CIDs) are applied, the capacitor voltage can

droop due to baseline wander (see Figure 20), causing pattern-

dependent jitter (PDJ).

The user must determine how much droop is tolerable and

choose an ac coupling capacitor based on that amount of droop.

The amount of PDJ can then be approximated based on the

capacitor selection. The actual capacitor value selection may

require some trade-offs between droop and PDJ.

Example: Assuming that 2% droop can be tolerated, then the

maximum differential droop is 4%. Normalizing to Vpp:

Droop = ∆ V = 0.04 V = 0.5 Vpp (1 − e–t/τ) ; therefore, τ = 12t

where:

τ is the RC time constant (C is the ac coupling capacitor, R =

100 Ω seen by C).

t is the total discharge time, which is equal to nΤ.

n is the number of CIDs.

T is the bit period.

The capacitor value can then be calculated by combining the

equations for τ and t:

C = 12nT/R

Once the capacitor value is selected, the PDJ can be

approximated as

( ) PDJ pspp = 0.5t r 1 − e (−nT/RC) / 0.6

where:

PDJpspp is the amount of pattern-dependent jitter allowed;

< 0.01 UI p-p typical.

tr is the rise time, which is equal to 0.22/BW,

where BW ~ 0.7 (bit rate).

Note that this expression for tr is accurate only for the inputs.

The output rise time for the ADN2816 is ~100 ps regardless of

data rate.

Rev. PrA | Page 21 of 27

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