ADN2816XCPZ View Datasheet(PDF) - Analog Devices
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ADN2816XCPZ Datasheet PDF : 27 Pages
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Preliminary Technical Data
ADN2816
Table 6. Internal Register Map1
Reg Name R/W Address
FREQ0
R
0x0
FREQ1
R
0x1
FREQ2
R
0x2
RATE
R
0x3
MISC
R
0x4
CTRLA
W
0x8
CTRLB
W
0x9
CTRLC
W
0x11
D7
D6
D5
MSB
MSB
0
MSB
COARSE_RD[8] MSB
x
x
x
FREF range
Config Reset
LOL MISC[4]
0
0
System
reset
0
D4
D3
D2
Coarse datarate readback
Static
LOL
LOL
status
Datarate
measure
complete
Datarate/DIV_FREF ratio
0
Reset
MISC[2]
0
0
0
0
1 All writeable registers default to 0x00.
D1
D0
LSB
LSB
LSB
COARSE_RD[1]
x
COARSE_
RD[0] LSB
Measure
datarate
Lock to
reference
0
0
Squelch
mode
0
Table 7. Miscellaneous Register, MISC
D7 D6 D5
xxx
Static LOL
D4
0 = Waiting for next LOL
1 = Static LOL until reset
LOL Status
D3
0 = Locked
1 = Acquiring
Datarate Measurement
Complete
D2
D1
0 = Measuring datarate
x
1 = Measurement complete
Coarse Rate
Readback LSB
D0
COARSE_RD[0]
Table 8. Control Register, CTRLA1
FREF Range
Datarate/Div_FREF Ratio
D7 D6
D5 D4 D3 D2
0 0 12.3 MHz to 25 MHz 0 0 0 0 1
0 1 25 MHz to 50 MHz
00012
1 0 50 MHz to 100 MHz 0 0 1 0 4
1 1 100 MHz to 200 MHz
n
2n
1 0 0 0 256
Measure Datarate
D1
Set to 1 to measure datarate
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
1 Where DIV_FREF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
System Reset
Reset MISC[2]
D7
D6
D5
D4
D3
D2
D1
D0
0 = LOL pin normal operation Write a 1 followed by Write a 1 followed by Set
Write a 1 followed by Set
Set
Set
1 = LOL pin is static LOL
0 to reset MISC[4]
0 to reset ADN2816 to 0 0 to reset MISC[2]
to 0 to 0 to 0
Table 10. Control Register, CTRLC
D7
Set to 0
D6
Set to 0
D5
Set to 0
D4
Set to 0
D3
Set to 0
D2
Set to 0
Squelch Mode
D1
0 = Squelch CLK and DATA
1 = Squelch CLK or DATA
D0
Set to 0
Rev. PrA | Page 11 of 27
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