D4564163G5 View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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D4564163G5

64M-bit Synchronous DRAM 4-bank, LVTTL

Elpida Memory, Inc 

µPD4564441, 4564841, 4564163

Write command

(/CS, /CAS, /WE = Low, /RAS = High)

If the mode register is in the burst write mode, this command sets the

burst start address given by the column address to begin the burst write

operation. The first write data in burst mode can input with this

command with subsequent data on following clocks.

Fig.4 Column address and write

command

CLK

CKE

/CS

/RAS

/CAS

/WE

A12, A13

(Bank select)

A10

Add

H

Col.

Read command

(/CS, /CAS = Low, /RAS, /WE = High)

Read data is available after /CAS latency requirements have been met.

This command sets the burst start address given by the column

address.

Fig.5 Column address and read

command

CLK

CKE

/CS

/RAS

/CAS

/WE

A12, A13

(Bank select)

A10

Add

H

Col.

CBR (auto) refresh command

(/CS, /RAS, /CAS = Low, /WE, CKE = High)

This command is a request to begin the CBR (auto) refresh operation.

The refresh address is generated internally.

Before executing CBR (auto) refresh, all banks must be precharged.

After this cycle, all banks will be in the idle (precharged) state and

ready for a row activate command.

During tRC period (from refresh command to refresh or activate

command), the µPD4564xxx cannot accept any other command.

Fig.6 CBR (auto) refresh command

CLK

CKE H

/CS

/RAS

/CAS

/WE

A12, A13

(Bank select)

A10

Add

12

Data Sheet E0149N10

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