AT27LV520-70SU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

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AT27LV520-70SU

512K (64K x 8) Multiplexed Addresses/ Outputs Low-voltage OTP EPROM

Atmel Corporation 

AT27LV520

9. AC Characteristics for Read Operation

VCC = 3.0V to 3.6V and 4.5V to 5.5V

Symbol

tACC(3)

tCE

tAS

tAH

tALE

tOE(3)

tDF(4)(5)

tOH

Parameter

Address to Output Delay

Address Latch Enable Low to Output Delay

Address Setup Time

Address Hold Time

Address Latch Enable Width

OE/VPP to Output Delay

OE/VPP High to Output Float

Output Hold from Address or OE/VPP,

Whichever Occurred First

Condition

ALE = OE/VPP = VIL

Address Valid

OE/VPP = VIH

OE/VPP = VIH

OE/VPP = VIH

ALE = VIL

ALE = VIL

ALE = VIL

AT27LV520-70

Min

Max

70

55

12

12

40

30

25

7

AT27LV520-90

Min

Max

90

70

15

15

45

35

25

0

Units

ns

ns

ns

ns

ns

ns

ns

ns

10. AC Waveforms for Read Operation(1)

tALE

ALE

OE/VPP

AD7 - AD0

tCE

tDF

tAS

tAH

tOE

tOH

ADDRESS IN

DATA OUT

tACC

A15 - A8

Notes:

1. Timing measurement reference levels for all speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are

VIL = 0.45V and VIH = 2.4V.

2. OE/VPP may be delayed up to tCE - tOE after the address is valid without impact on tCE.

3. OE/VPP may be delayed up to tACC - tOE after the address is valid without impact on tACC.

4. This parameter is only sampled and is not 100% tested.

5. Output float is defined as the point when data is no longer driven.

5

0911G–EPROM–8/07

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