VP5313 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

View to exact match

VP5313

NTSC/PAL Digital Video Encoder

Zarlink Semiconductor Inc 

VP5313/VP5513

SDA

SCL

SA

RESETB

TTXDATA

TTXREQ

I2C INTERFACE

TELETEXT

CONTROL

TELETEXT

SHAPING

FILTER

SET-UP

REGISTERS

ANTI-TAPING

CONTROL

YCrCb

YCrCb to

RGB

YCrCb

8 INPUT YUV

DEMUX

PD7-0

INTERPOLATING

FILTERS

Y

UV

PXCK

HSYNC

VSYNC

FC0-2

3

COMPSYNC

CLAMP

VIDEO TIMING GENERATOR

REFSQ

SCSYNC

PALID

DIGITAL

PHASE COMP

+

+

SYNC

INSERT

MODULATOR

COLOUR SUBCARRIER

GENERATOR

Figure 2 Functional block diagram

CLOSED

CAPTION

MUX

9 BIT

DAC

9 BIT

DAC

G/Y

B/CVBS2

R/C

9 BIT

DAC

9 BIT

DAC

CVBS1

DAC

REF

RREF

VREF

DACCOMP

V

W

H

Peak Glitch Area = H x W/2

The glitch energy is calculated by measuring the area under the voltage

time curve for any LSB step, typically specified in picoVolt-seconds (pV-s)

T(ps)

Figure 3 Glitch Energy (see Peak Glitch Energy in table on page 2)

5

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