MC74HC160A View Datasheet(PDF) - ON Semiconductor
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MC74HC160A Datasheet PDF : 12 Pages
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MC74HC160A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
− 55 to
V
25°C
v 85°C v 125°C Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)*
(Figures 3 and 8)
2.0
6.0
4.8
4.0
MHz
4.5
30
24
20
6.0
35
28
24
tPLH
Maximum Propagation Delay, Clock to Q
(Figures 3 and 8)
2.0
170
215
255
ns
4.5
34
43
51
6.0
29
37
43
tPHL
2.0
205
255
310
4.5
41
51
62
6.0
35
43
53
tPHL
Maximum Propagation Delay, Reset to Q (HC160A Only)
(Figures 4 and 8)
2.0
210
265
315
ns
4.5
42
53
63
6.0
36
45
54
tPLH
Maximum Propagation Delay, Enable T to Ripple Carry Out
(Figures 5 and 8)
2.0
160
200
240
ns
4.5
32
40
48
6.0
27
34
41
tPHL
2.0
195
245
295
4.5
39
49
59
6.0
33
42
50
tPLH
Maximum Propagation Delay, Clock to Ripple Carry Out
(Figures 3 and 8)
2.0
175
220
265
ns
4.5
35
44
53
6.0
30
37
45
tPHL
2.0
215
270
325
4.5
43
54
65
6.0
37
46
55
tPHL
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC160A Only)
(Figures 4 and 8)
2.0
220
275
330
ns
4.5
44
55
66
6.0
37
47
56
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 8)
2.0
75
4.5
15
6.0
13
95
110
ns
19
22
16
19
Cin
Maximum Input Capacitance
−
10
10
10
pF
*Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out
propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable.
See Applications Information in this data sheet.
CPD
Power Dissipation Capacitance (Per Package)*
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
Typical @ 25°C, VCC = 5.0 V
60
pF
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