MC74HC160A
LOAD
TYPICAL APPLICATIONS CASCADING
INPUTS
INPUTS
INPUTS
H = COUNT
L = DISABLE
H = COUNT
L = DISABLE
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RIPPLE
CARRY
OUT
R Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RIPPLE
CARRY
OUT
R Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RIPPLE
CARRY
OUT
R Q0 Q1 Q2 Q3
TO
MORE
SIGNIFICANT
STAGES
RESET
CLOCK
OUTPUTS
OUTPUTS
OUTPUTS
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend
on number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Figure 10. N−Bit Synchronous Counters
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
CLOCK
RESET
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RIPPLE
CARRY
OUT
R Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RIPPLE
CARRY
OUT
R Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RIPPLE
CARRY
OUT
R Q0 Q1 Q2 Q3
TO
MORE
SIGNIFICANT
STAGES
OUTPUTS
OUTPUTS
Figure 11. Nibble Ripple Counter
OUTPUTS
ORDERING INFORMATION
Device
Package
Shipping†
MC74HC160ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC160ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74HC160ADTG
TSSOP−16*
96 Units / Rail
MC74HC160ADTR2G
TSSOP−16*
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
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