SP8400 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
View to exact match
SP8400 Datasheet PDF : 5 Pages
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SP8400
VCC
TTL/CMOS
MODULUS
CONTROL
1nF
50R
RF
SIGNAL
GENERATOR
TTL/CMOS
MODULUS
CONTROL
1nF 10nF
1
28
2
27
3
26
4
25
5
24
6
23
7 SP8400 22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
1nF
2x330R
OUTPUT
220nF
10nF
50R
Fig.4 Test circuit
APPLICATIONS INFORMATION
Circuit description, synthesiser divider
The divider is based on a divide by 8/9 modulus
prescaler, and a 12 stage control counter. This gives minimum
fractional – N division ratio of 64 (56 for general division), and
a maximum division ratio of 4103. The inputs to the control
counter are TTL/CMOS compatible. There is a fixed offset of
8 between the number on the data lines and the actual division
ratio.
The output is one transition only per divide cycle. This
eliminates the problem of where to put the redundant edge
when the divider is used in a fractional–N system, and also
avoids the problem of how to define the output pulse width.
This means that the overall division ratio conventionally de-
fined in terms of the rate of edges of the same polarity is twice
the selected division ratio.
Equations for division
The M and A data inputs form a 12 bit number with A0
being the least significant bit and M8 being the most significant
bit.
Definition 1: Division ratio – (input frequency to out
put edges, positive or negative).
= Number loaded + 8
Definition 2: Division ratio – (input frequency to out
put frequency).
= (Number loaded + 8) x 2
3
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