SST89C54-33-I-PJ View Datasheet(PDF) - Silicon Storage Technology
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SST89C54-33-I-PJ Datasheet PDF : 50 Pages
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FlashFlex51 MCU
SST89C54 / SST89C58
Preliminary Specifications
NOTES:
1. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due to
external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1 -to- 0 transitions during bus operations. In the worst
cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE
with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
2. Capacitive loading on Ports 0 & 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the
address bits are stabilizing.
3. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when Vin is approximately 2V.
4. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs= 80pF.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
15mA
Maximum IOL per 8-bit port:
26mA
Maximum IOL total for all outputs:
71mA
If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
7. See Figures 22, 23, 24 and 25 for test conditions. Minimum VDD for Power Down is 2.7V.
VDD
RST
VDD
VDD
IDD
VDD
P0
EA#
8XC5X
CLOCK (NC)
SIGNAL
XTAL2
XTAL1
VSS
All other pins disconnected
344 ILL F26.0
CLOCK (NC)
SIGNAL
VDD
VDD
IDD
VDD
P0
RST
EA#
8XC5X
XTAL2
XTAL1
VSS
All other pins disconnected
344 ILL F24.0
FIGURE 22: IDD TEST CONDITION, ACTIVE MODE
FIGURE 23: IDD TEST CONDITION, IDLE MODE
(NC)
VDD = 3 or 5V VDD
IDD
VDD
VDD
P0
RST
EA#
8XC5X
XTAL2
XTAL1
VSS
All other pins disconnected
344 ILL F25.2
FIGURE 24: IDD TEST CONDITION, POWER DOWN MODE
(NC)
VDD = 5V
VDD
IDD
VDD
VDD
P0
RST
EA#
8XC5X
XTAL2
XTAL1
VSS
All other pins disconnected
344 ILL F33.3
FIGURE 25: IDD TEST CONDITION, STANDBY (STOP CLOCK)
MODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
© 2000 Silicon Storage Technology, Inc.
41
344-2 8/00
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