ADUC814BRU View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
ADUC814BRU Datasheet PDF : 72 Pages
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Parameter
Oscillator Powered Down16
Wake-Up with INT0 Interrupt
Wake-Up with SPI/I2C Interrupt
Wake-Up with External RESET
After External RESET in Normal Mode
After WDT Reset in Normal Mode
FLASH/EE MEMORY RELIABILITY
CHARACTERISTICS17
Endurance18
Data Retention19
POWER REQUIREMENTS20, 21
Power Supply Voltages
AVDD/DVDD – AGND
VDD = 5 V
150
150
150
3
3
100,000
100
4.5
5.5
Power Supply Currents, Normal Mode
DVDD Current14
5
4
AVDD Current14
1.7
DVDD Current
20
16
AVDD Current
1.7
DVDD Current14
3.5
2.8
AVDD Current
1.7
Power Supply Currents, Idle Mode
DVDD Current14
1.7
1.5
AVDD Current14
0.15
DVDD Current14
6
4
AVDD Current14
0.15
DVDD Current14
1.25
1.1
AVDD Current14
0.15
Power Supply Currents, Power-Down
Mode
DVDD Current14
40
AVDD Current
1
DVDD Current
20
AVDD Current
1
Typical Additional Power Supply
Currents
PSM Peripheral
50
ADC
1.5
DAC
150
VDD = 3 V
400
400
400
3
3
Unit
ms typ
ms typ
ms typ
ms typ
ms typ
100,000
100
Cycles min
Years min
2.7
V min
3.3
V max
V min
V max
2.5
mA max
2
mA typ
1.7
mA max
10
mA max
8
mA typ
1.7
mA max
1.5
mA max
1.2
mA typ
1.7
mA max
1.2
mA max
1
mA typ
0.15
mA max
3
mA max
2.5
mA typ
0.15
mA max
1
mA max
0.7
mA typ
0.15
mA max
20
µA max
14
µA typ
1
µA typ
15
µA max
10
µA typ
1
µA typ
µA typ
mA typ
µA typ
ADuC814
Test Conditions
OSC_PD = 1 in PLLCON SFR
Controlled via WDCON SFR
AVDD/DVDD = 3 V nom
AVDD/DVDD = 5 V nom
Core CLK = 2.097 MHz
(CD bits in PLLCON = 3)
Core CLK = 16.78MHz (max)
(CD bits in PLLCON = 0)
Core CLK = 131.2 kHz (min)
(CD bits in PLLCON = 7)
Core CLK = 2.097 MHz
(CD Bits in PLLCON = 3)
Core CLK = 16.78 MHz (max)
(CD bits in PLLCON = 0)
Core CLK = 131 kHz (min)
(CD bits in PLLCON = 7)
Core CLK = 2.097 MHz or 16.78 MHz (CD bits in
PLLCON = 3 or 0)
Oscillator on
Oscillator off
Core CLK = 2.097 MHz, (CD bits in PLLCON = 3)
AVDD = DVDD = 5 V
Rev. A | Page 7 of 72
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