ADUC814BRU View Datasheet(PDF) - Analog Devices

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ADUC814BRU

MicroConverter®, Small Package 12-Bit ADC with Embedded Flash MCU

Analog Devices 

ADuC814

SPECIAL FUNCTION REGISTERS

All registers, except the program counter and the four general-

purpose register banks, reside in the SFR area. The SFR registers

include control, configuration, and data registers that provide an

interface between the CPU and all on-chip peripherals.

Figure 22 shows a full SFR memory map and SFR contents on

RESET; NOT USED indicates unoccupied SFR locations.

Unoccupied locations in the SFR address space are not

implemented, i.e., no register exists at this location. If an

unoccupied location is read, an unspecified value is returned.

SFR locations reserved for future use are shaded (RESERVED)

and should not be accessed by the user software.

ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR05 BITS

FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0

BITS

F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0

D1 D1EN D0

D0EN

BITS

EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0

E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0 BITS

ADCI ADCSPI CCONV SCONV CS3 CS2 CS1 CS0

DFH

0 DEH

0 DDH

0 DCH

0 DBH

0 DAH 0 D9H

0 D8H

BITS

0

CY

AC

F0

RS1 RS0 OV

FI

P

BITS

D7H 0 D6H 0 D5H 0 D4H 0 D3H 0 D2H 0 D1H 0 D0H 0

TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 BITS

CFH 0 CEH 0 CDH 0 CCH 0 CBH 0 CAH 0 C9H 0 C8H 0

PRE3 PRE2 PRE1 PRE0 WDIR WDS WD WDWR BITS

C7H 0 C6H 0 C5H 0 C4H 1 C3H 0 C2H 0 C1H 0 C0H 0

PSI PADC PT2

PS

PT1 PX1 PT0 PX0 BITS

BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH 0 B9H 0 B8H 0

RD

WR

T1

T0

INT1 INT0 TxD RxD BITS

B7H 1 B6H 1 B5H 1 B4H 1 B3H 1 B2H 1 B1H 1 B0H 1

EA EADC ET2

ES

ET1 EX1 ET0 EX0 BITS

AFH 0 AEH 0 ADH 0 ACH 0 ABH 0 AAH 0 A9H 0 A8H 0

SM0 SM1 SM2 REN TB8 RB8

TI

RI BITS

9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 0 98H 0

T2EX T2 BITS

97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H 1 90H 1

TF1 TR1 TF0 TR0 IE1

IT1

IE0

IT0 BITS

8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0

SPICON1 DAC0L

DAC0H

DAC1L

DAC1H DACCON

RESERVED RESERVED

F8H 04H F9H 00H FAH 00H FBH 00H FCH 00H FDH 04H

B1

ADCOFSL ADCOFSH ADCGAINL ADCGAINH ADCCON3

SPIDAT

RESERVED

F0H 00H F1H 00H F2H 20H F3H 00H F4H 00H F5H 00H

F7H 00H

DCON1

ADCCON1

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

E8H 00H

EFH 00H

ACC1

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

E0H 00H

ADCCON21 ADCDATAL ADCDATAH

PSMCON

RESERVED RESERVED RESERVED RESERVED

D8H 00H D9H 00H DAH 00H

DFH DEH

PSW1

PLLCON

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

D0H 00H

D7H 53H

T2CON1

RCAP2L RCAP2H

RESERVED

TL2

TH2

RESERVED RESERVED

C8H 00H

CAH 00H CBH 00H CCH 00H CDH 00H

WDCON1

CHIPID

EDARL

RESERVED

RESERVED NOT USED RESERVED

RESERVED

C0H 10H

C2H 0XH

C6H 00H

IP1

ECON ETIM1 ETIM2 EDATA1 EDATA2 EDATA3 EDATA4

B8H 00H B9H 00H BAH 00H BBH 00H BCH 00H BDH 00H BEH 00H BFH 00H

P31

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED NOT USED

B0H FFH

IE1

A8H 00H

IEIP2

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

A9H A0H

NOT USED TIMECON HTHSEC

SEC

MIN

HOUR

INTVAL

NOT USED

A1H 00H A2H 00H A3H 00H A4H 00H A5H 00H A6H 00H

SCON1

98H 00H

SBUF

99H 00H

I2CDAT

9AH 00H

I2CADD CFG814

NOT USED NOT USED NOT USED

9BH 55H 9CH 04H

P11,2

90H FFH

NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED

TCON 1 TMOD

TL0

TL1

TH0

TH1

RESERVED RESERVED

88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 00H

SP

NOT USED

DPL

DPH

PCON

RESERVED RESERVED RESERVED

81H 07H 82H 00H 83H 00H

87H 00H

SFR MAP KEY:

THESE BITS ARE CONTAINED IN THIS BYTE.

MNEMONIC

SFR ADDRESS

IE0 IT0

89H 0 88H 0

TCON

88H 00H

MNEMONIC

DEFAULT VALUE

DEFAULT VALUE

SFR ADDRESS

Figure 22. Special Function Register Locations and Reset Values

Note the following about SFRs:

• SFRs whose address ends in 0H or 8H are bit addressable.

• Only P1.0 and P1.1 can operate as digital I/O pins. P1.2–P1.7 can be configured as analog inputs (ADC inputs) or as digital inputs.

• The CHIPID SFR contains the silicon revision ID byte and may change for future silicon revisions.

• These registers are reconfigured at power-on with factory calculated calibration coefficients that can be overwritten by user code. See

the calibration options in ADCCON3 SFR.

• When the SPIM bit in the SPICON SFR is cleared, the SPR0 bit reflects the level on the SS pin (Pin 22).

Rev. A | Page 20 of 72

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