SAA8110G/C1 View Datasheet(PDF) - Philips Electronics

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SAA8110G/C1

Digital Signal Processor (DSP) for cameras

Philips Electronics 

Philips Semiconductors

Digital Signal Processor (DSP) for

cameras

Preliminary specification

SAA8110G

Analog output preprocessing

This block contains several features:

• Delay compensation for the luminance signal

• Up-sampling of the UV signal

• PAL/NTSC encoding

• YUV to RGB conversion

• Selection of the required analog output format (RGB,

YUV, YC or CVBS).

The analog outputs are given by three voltage DACs in

RGB or YUV or CVBS or YC format. Channels Y and G

include the sync information. Over-sampling at twice fclk is

made so that external filtering becomes easier. It is also

possible to have an adjustment of the subcarrier via the

serial interface. When CVBS output is used, chrominance

range is halved compared to luminance.

Measurement engine

The measurement engine performs measurements on

some selectable internal signals on frame/field basis and

prepares data for auto exposure, auto focus and auto

white balance processing. It uses an internal RAM

work-space for its control and data handling operations.

The contents of the work-space can be accessed via the

serial interface.

Vertical/horizontal reference and window timing and

control

The SAA8110G uses two vertical and horizontal

synchronization input signals (VSYNCIN and HSYNCIN) to

derive internal vertical and horizontal reference signals.

Besides a Field Identification input (FIIN) signal is required.

The timing of the vertical and horizontal input signals

should be such that:

1. The pixel frequency (CLK1) must be line-locked to the

line frequency of HSYNCIN: the number of clock

periods between two HSYNCIN pulses must be a fixed

integer number. The HSYNCIN should be at least one

clock period active HIGH.

2. The VSYNCIN signal indicates the start of a field

(or frame in case of progressive scanning); this

signal is also required for non-interlaced applications.

The VSYNCIN should be at least one clock period

HIGH.

3. The FIIN pulse indicates the phase of the field in case

of interlaced applications (FIIN = 0 means odd field).

Serial interface

The serial interface can either be an I2C-bus or a 80C51

UART (SNERT) (selectable with the SIS pin). Via the serial

interface the external microcontroller can control the

internal settings of the SAA8110G and read/write from/to

the internal RAM work-space linked to the measurement

engine (see list of parameter settings in

Chapter “Programming”). Some of the registers are

double-buffered to prevent that the change of control data

becomes visible on the output display.

Miscellaneous functions

A three wire bus is used to send 10-bit settings from a

microcontroller to the TDA8786 via the SAA8110G

registers.The SAA8110G supplies picture parameters and

needs some configuration parameters. Those values are

contained in registers and are updated during every

vertical synchronization pulse.

Mode control

This block controls the operation mode of the SAA8110G.

As described in Table 2, four modes may be selected:

depending on power reduction and I2C-bus timing.

Power dissipation management

The power dissipation of the SAA8110G will depend on the

required activity for a certain application. It is possible to

switch off via the serial interface unconcerned parts for a

given application. When an analog output is not used, the

power voltage pin of the DAC can be connected to ground

to limit the power consumption.

Clock configurations

Following conditions must be fulfilled:

• CLK1 should be generated as divide-by-two from CLK2

• The RESET pin should not go LOW before CLK1 and

CLK2 are both HIGH or LOW.

Table 2 SAA8110G mode control

T2 T1 T0

000

001

010

011

MODE

POWER

to(h)

REDUCTION I2C-BUS

application on

mode on

short

long

off

short

off

long

1997 Jun 13

15

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