VV6501 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

View to exact match

VV6501

VGA CMOS Color Image Sensor

STMicroelectronics 

VV6501

Functional Description

Dark calibration algorithm

The dark line monitoring logic accumulates a number of dark pixels, calculates an average and then

compares this average with the appropriate black level. There is a bit in serial register 45 which

determines whether the offset applied is the user-programmable value from serial register 44, or the

value calculated by the offset cancellation processor.

The dark offset cancellation algorithm accumulates data from the dark lines which is input to a leaky

integrator and an appropriate offset is calculated.

Following an exposure/gain change, on power up or when going out of suspend mode, the history in

the dark calibration leaky integrator is reset to the incoming value as the previously stored value will

be out of date.

User control

The serial interface allows the user the following additional controls:

q Accumulate dark pixels, calculate dark pixel average and report, but do not apply anything to

data stream

q Accumulate dark pixels, calculate dark pixel average, report and apply internally calculated

offset to data stream

q Accumulate dark pixels, calculate dark pixel average and report, but apply a SIF supplied offset

3.1.10 Sensor clock and frame rate control

The frame rate is determined by both the input sensor clock and some additional registers under

user control.

Sensor clock

The sensor requires a single-ended clock input. A 24MHz clock is required to generate 30 frames

per second VGA images. The results is a pixel rate of 12MHz.

Slower frame rates

In order to achieve slower frame-rates the user has a number of options:

q increase the inter-frame time by adding blank line (via SIF register)

q apply a slower external clock

q divide down the external clock using the sensor internal clock divider (via SIF register)

Clock divider

The sensor contains a 4-bit register with which the user selects the clock divider setting (N). Table 5

gives the mapping between the clk_div value and the divider ratio.

Table 5: User programmable clock divider values

clk_div[3:0]

0000 [default]

0001

001X

010X

011X

100X

divide by

1

2

4

6

8

10

19/60

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