VP5513A View Datasheet(PDF) - Mitel Networks
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VP5513A Datasheet PDF : 19 Pages
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The horizontal line duration for PAL equates to 1728
CLK27M cycles and within each line there are 444 data bit
periods. The duration of 37 data bits (the smallest number
possible for an integer number of CLK27M cycles) therefore
equates to 144 CLK27M cycles.
To ensure that the average bit rate is 6.9375 MHz, 33 in
every 37 data bits will have a duration of 4 CLK27M cycles and
4 in every 37 data bits will have a duration of 3 CLK27M cycles.
Of the first 37 data bits in each line, bits 10, 19, 28 and 37 will
VP5313/VP5513
have a duration of 3 CLK27M cycles. The sequence will be
repeated for all subsequent 37 bit groups.
Master Reset
The VP5313/VP5513 must be initialised with RESET. This
is an asynchronous, active low signal and must be active for
a minimum of 200ns in order to reset the VP5313/VP5513.
The device resets to line 64, start of horizontal sync (i.e. line
blanking active). There is no on-chip power on reset circuitry.
CVBS/Y
TTX_DATA
textbit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TTXDD
434
434
TTX_REQ
NCO Adjustment
Figure 4 Teletext timing diagram
Standard
Lines/ Field
field freq. HZ
NTSC
525 59.94
PAL-B, G, H, I (d) 625 50
PAL-N (Argentina) 625 50
Number of
pixels/line
at 27MHz
1716
1728
1728
Horizontal
freq. kHz.
fH
15.734266
15.625000
15.625000
Subcarrier
freq. kHz.
fSC
3.57954545
fSC/fH
(455/2)
SC_ADJ
register
hex
xx
4.43361875 (1135/4+1/625) 9C
3.58205625 (917/4+1/625) 57
FREQ2-0
registers hex
87 C1 F1
A8 26 2B
87 DA 51
(d) = default
xx = don’t care.
Table.2 Line, field and subcarrier standards and register settings
The calculation of the FREQ register value is according to the following formula:-
FREQ = 226 x fSC/PXCK hex, where PXCK = 27.00MHz
NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ
value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the
SC_ADJ value of 9C required for PAL-B, D, G, H, I.
PXCK Input (27MHz)
HS
Nck=2
Nck=0
t SU; PD
t HD; PD
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3
Pixel Data Input (PD[7,0])
Figure 5 REC 656 interface with HS output timing
11
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