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V4374128C24VSG-10PC View Datasheet(PDF) - Mosel Vitelic Corporation

Part Name
Description
View to exact match
V4374128C24VSG-10PC
Mosel-Vitelic
Mosel Vitelic Corporation  Mosel-Vitelic
V4374128C24VSG-10PC Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MOSEL VITELIC
SPD-Table: (Continued)
Byte Num-
ber
Function Described
28
Minimum Row Active to Row Active Delay
tRRD
29
Minimum RAS to CAS Delay tRCD
30
Minimum RAS Pulse Width tRAS
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
35
SDRAM Data Input Hold Time
36-61
Superset Information (May be used in Fu-
ture)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65-71
Manufacturer’s JEDEC ID Code (cont.)
72
Manufacturing Location
73-90
Module Part Number (ASCII)
91-92
PCB Identification Code
93
Assembly Manufacturing Date (Year)
94
Assembly Manufacturing Date (Week)
95-98
Assembly Serial Number
99-125 Reserved
126
Intel Specification for Frequency
127
Reserved
128+
Unused Storage Location
SPD Entry Value
14 ns/15 ns/16 ns
15 ns/20 ns
42 ns/45 ns
512 MByte
1.5 ns/2.0 ns
0.8 ns/1.0 ns
1.5 ns/2.0 ns
0.8 ns/1.0 ns
Revision 2/1.2
Mosel Vitelic
V4374128C24V
V4374128C24V
-75PC
0F
Hex Value
-75
0F
-10PC
0F
0F
14
14
2A
2D
2D
80
80
80
15
15
20
08
08
10
15
15
20
08
08
10
00
00
00
02
02
12
69
AD
1A
40
40
40
00
00
00
00
00
00
64
64
64
8D
8D
8D
00
00
00
V4374128C24V Rev. 1.1 January 2002
6

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