S83L196NP View Datasheet(PDF) - Intel

Part Name

Description

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S83L196NP

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Name

P4.3:0

PWM2:0

RD#

READY

RESET#

RPD

Table 6. Signal Descriptions (Continued)

Type

Description

I/O Port 4

This ia a 4-bit bidirectional, standard I/O port with high-current drive capability.

Port 4 shares package pins with the following signals: P4.0/PWM0, P4.1/PWM1,

and P4.2/PWM2. P4.3 has a dedicated package pin.

O Pulse Width Modulator Outputs

These are PWM output pins with high-current drive capability.

PWM2:0 share package pins with P4.2:0.

O Read

Read-signal output to external memory. RD# is asserted only during external

memory reads.

RD# shares a package pin with OE#. (While most signals that share package pins

are connected to the pin by programming their associated control registers, both of

these signals are always connected to the pin.)

I Ready Input

This active-high input can be used to insert wait states in addition to those

programmed in the chip configuration byte 0 (CCB0) and the bus control x register

(BUSCONx). CCB0 is programmed with the minimum number of wait states (0–3)

for an external fetch of CCB1, and BUSCONx is programmed with the minimum

number of wait states (0–3) for all external accesses to the address range assigned

to the chip-select x channel. If READY is low when the programmed number of wait

states is reached, additional wait states are added until READY is pulled high.

READY shares a package pin with P5.6.

I/O Reset

A level-sensitive reset input to and open-drain system reset output from the

microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-

down transistor connected to the RESET# pin for 16 state times. In the powerdown,

standby, and idle modes, asserting RESET# causes the chip to reset and return to

normal operating mode. After a device reset, the first instruction fetch is from

FF2080H (or F2080H in external memory). For the 80L196NP, the program and

special-purpose memory locations (FF2000–FF2FFFH) reside in external memory.

For the 83L196NP, these locations can reside either in external memory or in

internal ROM.

I Return from Powerdown

Timing pin for the return-from-powerdown circuit.

If your application uses powerdown mode, connect a capacitor between RPD and

VSS if the internal oscillator is the clock source.

The capacitor causes a delay that enables the oscillator and PLL circuitry to

stabilize before the internal CPU and peripheral clocks are enabled.

The capacitor is not required if your application uses powerdown mode and if an

external clock input is the clock source.

If your application does not use powerdown mode, leave this pin unconnected.

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