S83L196NP View Datasheet(PDF) - Intel

Part Name

Description

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S83L196NP

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Name

HOLD#

INST

NMI

ONCE

P1.7:0

P2.7:0

P3.7:0

Table 6. Signal Descriptions (Continued)

Type

Description

I Bus Hold Request

An external device uses this active-low input signal to request control of the bus.

When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can

function only as HOLD#, regardless of the configuration selected through the port

configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change

the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is

cleared).

HOLD# shares a package pin with P2.5.

O Instruction Fetch

When high, INST indicates that an instruction is being fetched from external

memory. The signal remains high during the entire bus cycle of an external

instruction fetch. INST is low for data accesses, including interrupt vector fetches

and chip configuration byte reads. INST is low during internal memory fetches.

I Nonmaskable Interrupt

In normal operating mode, a rising edge on NMI generates a nonmaskable

interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for

greater than one state time to guarantee that it is recognized.

I On-circuit Emulation

Holding ONCE high during the rising edge of RESET# places the device into on-

circuit emulation (ONCE) mode. This mode puts all pins into a high-impedance

state, thereby isolating the device from other components in the system. The value

of ONCE is latched when the RESET# pin goes inactive. While the device is in

ONCE mode, you can debug the system using a clip-on emulator.

To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent

inadvertent entry into ONCE mode, connect the ONCE pin to VSS.

I/O Port 1

This is a standard, 8-bit, bidirectional port that shares package pins with individually

selectable special-function signals.

Port 1 shares package pins with the following signals: P1.0/EPA0, P1.1/EPA1,

P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.

I/O Port 2

This is a standard, 8-bit, bidirectional port that shares package pins with individually

selectable special-function signals.

Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD,

P2.2/EXTINT0, P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and

P2.7/CLKOUT.

I/O Port 3

This is a standard, 8-bit, bidirectional port that shares package pins with individually

selectable special-function signals.

Port 3 shares package pins with the following signals: P3.0/CS0#, P3.1/CS1#,

P3.2/CS2#, P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and

P3.7/EXTINT3.

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