IDT72605(2013) View Datasheet(PDF) - Integrated Device Technology
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IDT72605 Datasheet PDF : 17 Pages
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IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
CLKB
(R/WA
ENB
= 0)
PAEBA
CLKA
(R/WA
ENA
= 1)
tCLKH
tCLKL
tCS
tCH
WRITE
n words in FIFO
tSKEW2(1)
tPAE
n+1 words in FIFO
tPAE
(2)
tCS
tCH
READ
2704 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
Figure 14. B→A Programmable Almost-Empty Flag Timing
CLKB
(R/WA
ENB
= 0)
PAFBA
CLKA
tCLKH
tCLKL
(2)
tCS
tCH
WRITE
Full - (m+1) words in FIFO
tPAF
Full - m words in FIFO
tSKEW2(1)
tPAF
(R/WA
ENA
= 1)
tCS
tCH
2704 drw 18
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 15. B→A Programmable Almost-Full Flag Timing
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