IDT72605(2013) View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

View to exact match

IDT72605
(Rev.:2013)

CMOS SyncBiFIFO 256 x 18 x 2 512 x 18 x 2

Integrated Device Technology 

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

INDUSTRIAL TEMPERATURE RANGE

CLKA

ENA

(R/WA = 0)

PAEAB

CLKB

ENA

(R/WB = 1)

tCLKH

tCLKL

tCS

tCH

WRITE

n words in FIFO

tSKEW2 (1)

tPAE

n+1 words in FIFO

tCS

tCH

READ

tPAE

(2)

2704 drw 15

NOTES:

1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the rising edge of CLKA and

the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge.

2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.

Figure 12. A→B Programmable Almost-Empty Flag Timing

tCLKH

tCLKL

(2)

CLKA

(R/WA

ENA

= 0)

tCS

tCH

WRITE

PAFAB

Full - (m+1) words in FIFO

tPAF

Full - m words in FIFO

tPAF

CLKB

(R/WB

ENB

= 1)

tCS

tCH

READ

2704 drw 16

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the rising edge of CLKB

and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge.

2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.

Figure 13. A→B Programmable Almost-Full Flag Timing

15

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