CDP1879 View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

CDP1879

CMOS Real-Time Clock

Intersil 

CDP1879, CDP1879C-1

TPA

ADDRESS

LATCH HIGH-ORDER

ADDRESS FOR CS

HIGH BYTE

LOW BYTE

TPB/WR

DATA LATCHED

DATA FROM CPU

TO REAL TIME CLOCK

VALID DATA

FIGURE 12. CDP1800 SERIES MEMORY MAPPED WRITE CYCLE TIMING WAVEFORMS

TPA

ADDRESS

RD

HIGH BYTE

LOW BYTE

OUTPUT DRIVERS

ENABLED DISABLED

DATA FROM

REAL TIME CLOCK

TO CPU

VALID DATA

FIGURE 13. CDP1800 SERIES MEMORY MAPPED READ CYCLE TIMING WAVEFORMS

ADDRESS

LINES

CLEAR

TPA

MRD

TPB

INTERRUPT

N0

N1

N2

MEMORY

CDP1802

XTAL

XTAL

RESET

TPA

CLOCK

OUT

RD

TPB/WR

INTERRUPT

A0

A1

A2

IO/MEM

CS

CDP1879

DB0 - DB7

VDD

FIGURE 14. TYPICAL CDP1802 INPUT/OUTPUT MAPPED SYSTEM

4-118

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