CDP1879 View Datasheet(PDF) - Intersil
Part Name
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CDP1879 Datasheet PDF : 18 Pages
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CDP1879, CDP1879C-1
STANDBY (TIMEKEEPING) CHARACTERISTICS AT FULL TEMPERATURE RANGE
LIMITS
PARAMETER
VDD
(V)
VSTBY
(V)
CDP1879
MIN
MAX
CDP1879C-1
MIN
MAX
Chip Deselect to Standby
tCSTBY
(Timekeeping) Voltage Time
5
2.5, 3
2
-
2
-
10
2.5, 3
1
-
-
-
Recovery to Normal
tRC
Operation Time
5
2.5, 3
2
-
2
-
10
2.5, 3
1
-
-
-
UNITS
µs
EXTERNAL CLOCK SOURCE OF 32kHz
TYPICAL STANDBY (TIMEKEEPING) VOLTAGE
3V (-40oC ≤ T ≤ +85oC)
2.5V (-0oC ≤ T ≤ +70oC
5
STANDBY
VOLTAGE MODE
VDD
tSTBY
CS
0.95 VDD VSTBY 0.95 VDD
tR (NOTE 1)
tF (NOTE 1)
tRC
VIH
VIH
VIL
VIL
NOTE:
1. tR, tF ≥ 1µs
FIGURE 8. STANDBY (TIMEKEEPING) VOLTAGE AND TIMING
WAVEFORMS
4
3
2
1
0-40
-20
0
20
40
60
80
100
FULL TEMPERATURE RANGE - oC
FIGURE 9. TYPICAL STANDBY (TIMEKEEPING) VOLTAGE vs
FULL TEMPERATURE RANGE
Applications
A typical application for this real-time clock is as a wake-up
control to a CPU to reduce total system power in intermit-
tent-use systems. A hookup diagram illustrating this feature
is shown in Figure 10. In this configuration, the alarm and
power-down features of the CDP1879 are utilized in the con-
trol of the sleep and wake-up states of the CPU. A typical
shut-down/start-up sequence for this system could proceed
as follows:
1. The CPU has finished a current task and will be inactive
for the next six hours.
2. The CPU loads the CDP1879 alarm registers with the
desired wake-up time.
3. The CDP1800 Q output is set high, which stops the CPU
oscillator (as an alternative, in an NMOS system, power
to all components except the clock chip could be shut off).
4. This Q output signal is received by the CDP1879 as a
power-down signal.
5. The CDP1879 three-states the interrupt output pin.
6. The CDP1879 eventually times out, and sets an alarm by
driving the INT output low.
7. The alarm signal resets the CPU (to avoid oscillator start-
up problems) and flags the processor for a warm-start
routine.
8. The CPU, once into its normal software sequence, writes
to the CDP1879 control register to reset the interrupt
request.
4-116
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