CDP1852 View Datasheet(PDF) - Intersil
Part Name
Description
View to exact match
CDP1852 Datasheet PDF : 9 Pages
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CDP1852, CDP1852C
CS1 - CS2
tSW
(NOTE 1)
CLOCK
DATA IN
tWW
tDH
DATA BUS
SR
tRSR
tDS
HIGH
IMPEDANCE
tCSR
tSDO
tDOH
tSSR
CLEAR
tCLR
NOTE 1. CS1 • CS2 is the overlap of CS1 = 1 and CS2 = 1.
MODE 0 TRUTH TABLE
SERVICE REQUEST TRUTH TABLE
CLOCK
X
† CS1-CS2
0
CLEAR
X
DATA OUT EQUALS
High Impedance
CLOCK
CS1 or CS2
or CLEAR
0
1
0
0
0
1
1
Data Latch
SR/SR 0
SR/SR 1
1
1
X
Data In
† CS1 • CS2: CS1 = 1, CS2 = 1
FIGURE 4. MODE 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES
MEMORY
ADDRESS
LINES
CDP1802
NX
MRD
EFX
VSS
CDP1852
CS2
CLOCK
CS1
D1
SR
MODE D0
STROBE
DATA FROM
PERIPHERAL
STROBE
PERIPHERAL
DATA
SR/SR
DATA BUS
PERIPHERAL DEVICE
PLACES DATA IN CDP1852
AND CDP1852 SIGNALS
CDP1802 THAT DATA IS READY
NX
MRD
DATA BUS
VALID
THREE - STATE
CDP1802 SELECTS
CDP1852 AND DATA
IS TRANSFERRED
TO MEMORY AND
THE MICROPROCESSOR
FIGURE 5. INPUT PORT MODE 0 FUNCTIONAL DIAGRAM AND WAVEFORMS - TYPICAL OPERATION
6
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