SAA4952WP View Datasheet(PDF) - Philips Electronics

Part Name

Description

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SAA4952WP

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Objective specification

SAA4952WP

VACQ

This is the 50 Hz vertical synchronization input signal

derived from a suitable vertical synchronization circuit

(i.e. TDA2579). The LOW-to-HIGH transition of this pulse

is the timing reference of all vertical control signals of the

SAA4952WP.

The vertical acquisition timing is illustrated in Fig.5. VWE1

is resynchronized with HWE1 internally. Nr and Nf can

represent values varying between 1 and 511, whereas Nf

should be programmed in accordance with the expected

field length (PAL 312, NTSC 262). If the incoming fields

are shorter than programmed the memory controller resets

VWE1 itself.

RSTW1

The reset write output pulse 1 starts the write address

pointer of field memory 1. The RSTW1 signal is derived

from the 50 Hz vertical acquisition pulse (VACQ) and has

a pulse width of 32 µs.

STROBE

The asynchronous, active HIGH, STROBE input controls

the input enable signal IE1 to memory 1 in the still picture

mode (see Section “IE1”).

Display and deflection part

LLD

The input signal LLD is a line-locked clock for the display

side of the memory controller.

In the event of a two-clock system the possible display

frequencies (27, 32 and 36 MHz) are derived from one

switchable external PLL. The internal system clocks LLD is

supplied via the input LLDFL. The input pin LLD is not used

and its level can be fixed. This configuration is foreseen for

applications using the TDA9152 or other deflection

controllers which do not need a clock supply.

In applications using the TDA9151 a 27 MHz clock is

always required. The system has to operate in a

three-clock mode. The deflection PLL generates the

27 MHz clock frequency only, whereas the display PLL

generates the 32 and 36 MHz in parallel, if conversion

modes are used which operate with these display

frequencies. If the display is operating with 27 MHz, LLD is

switched to the deflection PLL input and the third PLL can

be omitted. The 32 and 36 MHz PLL is synchronized on

the horizontal deflection pulse (HDFL). A digital feedback

signal (HRD) to the phase comparator is supplied by the

memory controller.

In the 50 Hz/1fH mode only one system clock is required.

The display, deflection and acquisition clocks are equal.

SRC

The display clock input signal from inputs LLD or LLDFL is

buffered in the memory controller. Depending on the

selected mode one of them is output as Serial Read Clock

(SRC) for the field memories. Additionally SRC is used as

a clock pulse for the writing of memory 2, the noise

reduction circuit NORIC and the back-end circuit BENDIC

or for PROZONIC (instead of NORIC) and the following

DAC.

HRD

The Horizontal Reference Display pulse (HRD) has a duty

cycle of 50% and a frequency of 32 kHz. HRD is the

reference pulse for the horizontal timing of the control

signals RE1, RE2, WE2, HD and BLND generated by the

display part of the SAA4952WP in the event of a

three-clock system with a selected display frequency of

32 or 36 MHz.

HVSP

The vertical display counter is incremented with every

HVSP pulse (see Fig.6). The HVSP signal is created from

the four pulses HVSP1 to HVSP4. The distance between

the pulses has to be programmed to 16 µs. The HVSP

signal is the equivalent to the HVACQS signal of the

vertical acquisition part. The HVSP1 pulse should be

programmed 32 µs after the HVACQS1 pulse. This

programming ensures that the vertical picture stability is

also kept in the event of unstable sources such as VCRs.

BLND

The output signal BLND is a horizontal blanking pulse and

is, for example, used for the peripheral circuits NORIC and

BENDIC. A LOW level indicates the blanking interval, a

HIGH level indicates valid data from the memories. It is

possible to delay the horizontal timing of BLND by up to

three LLD clock pulses.

WE2

A HIGH level on this output pin enables picture data to be

written to field memory 2. WE2 is a composite signal which

includes the horizontal write enable signal and the vertical

write enable signal. The horizontal timing of WE2 can be

delayed by up to three steps of LLD clock pulses.

1997 Jun 10

16

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