MAX512 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

View to exact match

MAX512

Low-Cost, Triple, 8-Bit Voltage-Output DACs with Serial Interface

Maxim Integrated 

Low-Cost, Triple, 8-Bit Voltage-Output DACs

with Serial Interface

Shutdown Mode

When programmed to shutdown mode, the outputs of

DAC A and B go into a high-impedance state. Virtually

no current flows into or out of the buffer amplifiers in

that state. The output of DAC C goes to 0V when shut

down. In shutdown mode, the REF_ inputs are high

impedance (2MΩ typ) to conserve current drain from

the system reference; therefore, the system reference

does not have to be powered down. The logic output

LOUT remains active in shutdown.

Coming out of shutdown, the DAC outputs return to the

values kept in the registers. The recovery time is equiv-

alent to the DAC settling time.

The R–—E—S—E—T– input is active low. When asserted (–R—RE—eS—sE—eT–t

= 0), DACs A and B are set to full scale (FFhex) and

active, while DAC C is set to zero code (00hex) and

active. The 16-bit serial register is cleared to 0000hex.

LOUT is reset to zero.

An

active-low

chip

select

(C–—S–)

Serial

enables the

Interface

shift register

to receive data from the serial data input. Data is

clocked into the shift register on every rising edge of

the serial clock signal (SCLK). The clock frequency can

be as high as 5MHz.

Data is sent MSB first and can be transmitted in one

1tim6-ebiwt hweonrdC–—. S–Thisekwepritteacctyivcele(lcoawn)

be interrupted at any

to allow, for example,

two 8-bit-wide transfers. After clocking all 16 bits into

Table 1. Input Shift Register

B0*

B1

B2

B3

B4

B5

B6

B7

LA

LB

LC

SA

SB

SC

Q1

Q2**

DAC Data Bit 0 (LSB)

DAC Data Bit 1

DAC Data Bit 2

DAC Data Bit 3

DAC Data Bit 4

DAC Data Bit 5

DAC Data Bit 6

DAC Data Bit 7 (MSB)

Load Reg DAC A, Active High

Load Reg DAC B, Active High

Load Reg DAC C, Active High

Shut Down DAC A, Active High

Shut Down DAC B, Active High

Shut Down DAC C, Active High

Logic Output

Uncommitted Bit

**Clocked in last.

**Clocked in first.

the input shift register, the rising edge of C–—S– updates

the DAC outputs, the shutdown status, and the status of

the logic output. Because of their single buffered struc-

ture, DACs cannot be simultaneously updated to differ-

ent digital values.

CS

SCLK

SDIN

Q2 Q1 SC SB SA LC LB LA

(CONTROL BYTE)

OPTIONAL

INSTRUCTION

EXECUTED

D7 D6 D5 D4 D3 D2 D1 D0

(DATA BYTE)

Figure 2. MAX512/MAX513 3-Wire Serial-Interface Timing Diagram

10 ______________________________________________________________________________________

Share Link: