M27V102 View Datasheet(PDF) - STMicroelectronics
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M27V102 Datasheet PDF : 15 Pages
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M27V102
Figure 6. Programming and Verify Modes AC Waveforms
A0-A15
Q0-Q15
VPP
VCC
E
P
G
tAVPL
DATA IN
tQVPL
VALID
tPHQX
DATA OUT
tVPHPL
tGLQV
tVCHPL
tELPL
tPLPH
tQXGL
PROGRAM
VERIFY
tGHQZ
tGHAX
AI00706
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n =0
NO
++n
= 25
YES
P = 100µs Pulse
NO
VERIFY
YES
++ Addr
FAIL
Last NO
Addr
YES
CHECK ALL WORDS
1st: VCC = 6V
2nd: VCC = 4.2V
AI00707C
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 6.5 seconds. Program-
ming with PRESTO II consists of applying a se-
quenceof 100 µs program pulses toeach word until
a correct verify occurs (see Figure 7). During pro-
gramming and verify operation, a MARGIN MODE
circuit is automaticallyactivated in order to guaran-
tee that each cell is programmed with enough
margin. No overprogrampulse is applied since the
verify in MARGIN MODE at VCC much higher than
3.6V provides necessary margin to each pro-
grammed cell.
Program Inhibit
Programming of multiple M27V102s in parallel with
different data is also easily accomplished. Except
for E, all like inputs including G of the parallel
M27V102 may be common. A TTL low level pulse
applied to a M27V102’sP input, with E low and VPP
at 12.75V, will program that M27V102. A high level
E input inhibits the other M27V102s from being
programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correctly
programmed. The verify is accomplished with E
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