LR38617 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

View to exact match

LR38617

Timing Generator IC for 3300 k/3 370 k-pixel CCDs

Sharp Electronics 

LR38617

Serial Data Control

SERIAL DATA INPUT TIMING

ED0

ED1

ED2

D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24

ED2 is shifted by the rising edge of ED1, and is

latched by the pulse #1 which is generated after

167 to 222 ns delay from the rising edge of ED0.

(See Fig. 2.)

The latched serial data are divided into two types

by the data of D00, and are relatched by the pulse

#2 which is generated after 277 to 332 ns delay

from the rising edge of ED0. (See Fig. 1.)

INMD is effective at the start of #3 horizontal line,

and shutter control data are effective at the start of

#6 or #234 horizontal line at CCD = L, or #12 HD

horizontal line at CCD = H, and other data are

effective at pulse #2.

ED0 should be at low level during data inputs of

ED1 and ED2, or while ACLX is at low level.

ED0

18 MHz

Pulse #1

Pulse #2

333 ns min.

166 ns

277 ns

Fig. 1 Data Latch Timing

Mode

VD

VH1AX

VH3AX

ED0

ED1

ED2

OFDC

Monitoring

from monitoring mode

to still mode

data input

period

10 ms min.

VD

HD

ED0

Still

Odd Field

Even Field

from still mode to monitoring mode

data input period

5 µs min.

5 µs min.

Fig. 2 Input Pulse Timing of ED0, ED1 and ED2

6

Monitoring

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