ISL97645A View Datasheet(PDF) - Intersil
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ISL97645A Datasheet PDF : 15 Pages
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ISL97645A
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rate for the display. Thus the
amplifier must be capable of sourcing and sinking capacitive
pulses of current, which can occasionally be quite large (a
few 100mA for typical applications).
The ISL97645A VCOM amplifier's output current is limited to
400mA. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable
operation of the part. It does not necessarily prevent a large
temperature rise if the current is maintained. (In this case the
whole chip may be shut down by the thermal trip to protect
functionality.) If the display occasionally demands current
pulses higher than this limit, the reservoir capacitor will
provide the excess and the amplifier will top the reservoir
capacitor back up once the pulse has stopped. This will
happen on the µs time scale in practical systems and for
pulses 2 or 3 times the current limit, the VCOM voltage will
have settled again before the next line is processed.
Fault Protection
ISL97645A provides the overall fault protections including
over current protection and over-temperature protection.
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
+140°C and +100°C respectively.
Layout Recommendation
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VIN and VDD bypass capacitors close to the pins.
3. Reduce the loop area with large AC amplitudes and fast
slew rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for control circuit.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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14
FN6353.0
July 2, 2007
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