IDT72805LB View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

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IDT72805LB

CMOS DUAL SyncFIFO DUAL 256 x 18 DUAL 512 x 18 DUAL 1,024 x 18 DUAL 4,096 x 18

Integrated Device Technology 

IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM

256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18

RCLK

tENS

REN

EF

Q0 - Q17

OE

WCLK

tCLKH

tCLK

tCLKL

tENH

tREF

tA

tOLZ

tOE

NO OPERATION

tSKEW1(1)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tREF

VALID DATA

tOHZ

WEN

NOTES:

3139 drw 07

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge

of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.

2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.

Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)

WCLK

tDS

D0 - D17

D0 (first valid write)

D1

D2

tENS

WEN

tSKEW1

tFRL(1)

RCLK

tREF

D3

D4

EF

tENS

REN

Q0 - Q17

tOLZ

tA

tA

D0

D1

tOE

OE

NOTES:

3139 drw 08

1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing

applies only at the Empty Boundary (EF = LOW).

2. The first word is available the cycle after EF goes HIGH, always.

3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.

Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)

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