IDT72805LB View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

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IDT72805LB

CMOS DUAL SyncFIFO DUAL 256 x 18 DUAL 512 x 18 DUAL 1,024 x 18 DUAL 4,096 x 18

Integrated Device Technology 

IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFOTM

256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18

WCLK

D0 - D17

FF

NO WRITE

1

(1)

tSKEW1

2

tDS

tWFF

Wd

tWFF

WEN

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NO WRITE

1

(1)

tSKEW1

2

tDS

DATA WRITE

tWFF

RCLK

REN

tENS

tENH

OE LOW

Q0 - Q17

tA

DATA IN OUTPUT REGISTER

tENS

tENH

tA

DATA READ

NEXT DATA READ

3139 drw 24

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.

2. LD = HIGH.

3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.

Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)

WCLK

D0 - D17

WEN

FF

RCLK

REN

tCLKH

1

tCLK

tCLKL

tSKEW1(1)

2

tDS

DATA IN VALID

tENS

tWFF

tDH

tENH

tWFF

NO OPERATION

3139 drw 25

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising edge

of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra WCLK cycle.

2. LD = HIGH.

3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.

Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)

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