ICM-102ASA View Datasheet(PDF) - Unspecified
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ICM-102ASA Datasheet PDF : 15 Pages
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ICM102A CIF CMOS sensor
Data Sheet Version1.0 July 2002
1. Pin Assignment
Pin #
14
11
12
13
34
36
32
33
2
1
10
16
8
48
47
46
44
41
39
38
37
3
5
35
15
7, 31
9, 30
19
17
Name
CLKSEL
CLKIN
XIN
XOUT
PCLK
OEN
SIFID
MSSEL
SCL
SDA
POWERDN
RSET
RSTN
DOUT[7]
DOUT[6]
DOUT[5]
DOUT[4]
DOUT[3]
DOUT[2]
DOUT[1]
DOUT[0]
HSYNC
VSYNC
FLASH
RAMP
VDDA
GNDA
VDDD
GNDD
Class*
D, I, N
D, I, N
A, I
A, O
D, O
D, I, N
D, I, N
D, I, U
D,
I/O
D,
I/O
D, I, N
A, I
D, I, U
D, O
D,
I/O
D,
I/O
D,
I/O
D,
I/O
D,
I/O
D,
I/O
D,
I/O
D,
I/O
D,
I/O
D, O
A, O
P
P
P
P
Function
Clock source selection. 0: internal oscillator, 1:
CLKIN
External clock source
Oscillator in
Oscillator out
Pixel clock output
Output enable. 0: enable, 1: disable
Lsb of SIF slave address
SIF master/slave selection. 0: slave, 1: master
SIF clock
SIF data
Power down control, 0: power down, 1: active
Resistor to ground = 39 KΩ @ 12 MHz main clock
Chip reset, active low
Data output bit 7
Data output bit 6; if pulled up/down, the initial
value of TIMING_CONTROL_LOW[2] (VSYNC
polarity) is 1/0
Data output bit 5; if pulled up/down, the initial
value of TIMING_CONTROL_LOW[1] (HSYNC
polarity) is 1/0
Data output bit 4; if pulled up/down, the initial
value of AD_IDL[3] (Sub ID) is 1/0
Data output bit 3; if pulled up/down, the initial
value of AD_IDL[2] (Sub ID) is 1/0
Data output bit 2; if pulled up/down, the initial
value of AD_IDL[1] (Sub ID) is 1/0
Data output bit 1; if pulled up/down, the initial
value of AD_IDL[0] (Sub ID) is 1/0
Data output bit 0; if pulled up/down, the
synchronization mode is in master/slave mode
which requires HSYNC and VSYNC operating in
output/input mode
Horizontal sync signal
Vertical sync signal
Flash light control
Analog ramp output
Sensor analog power
Sensor analog ground
Sensor digital power
Sensor digital ground
©2000, 2001, 2002 IC Media Corporation & IC Media Technology Corp.
web site: http://www.ic- media.com/
web site: http://www.ic- media.com.tw/
page 4
7/24/2002
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