EDS1232AATA-60TI View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

View to exact match

EDS1232AATA-60TI

128M bits SDRAM WTR (Wide Temperature Range)

Elpida Memory, Inc 

EDS1232AATA-TI

Current state

/CS /RAS /CAS /WE Address

Command

Operation

Write recovering H × × × ×

DESL

Nop → Enter row active after tDPL

L HHH×

NOP

Nop → Enter row active after tDPL

L HHL ×

BST

Nop → Enter row active after tDPL

L H L H BA, CA, A10 READ/READA Start read, Determine AP

L H L L BA, CA, A10 WRIT/ WRITA New write, Determine AP

L L H H BA, RA

ACT

ILLEGAL

L L H L BA, A10

PRE/PALL

ILLEGAL

L L L H×

REF/SELF

ILLEGAL

L L L L OPCODE

Write recovering H × × × ×

MRS

DESL

ILLEGAL

Nop → Enter precharge after tDPL

with auto

L HHH×

NOP

Nop → Enter precharge after tDPL

precharge

L HHL ×

BST

Nop → Enter row active after tDPL

L H L H BA, CA, A10 READ/READA ILLEGAL

L H L L BA, CA, A10 WRIT/WRITA ILLEGAL

L L H H BA, RA

ACT

ILLEGAL

L L H L BA, A10

PRE/PALL

ILLEGAL

L L L H×

REF/SELF

ILLEGAL

Refresh

L L L L OPCODE

H× × × ×

MRS

DESL

ILLEGAL

Nop → Enter idle after tRC

L HHH×

NOP/BST

Nop → Enter idle after tRC

L HHL ×

READ/READA ILLEGAL

L HL H×

ACT/PRE/PALL ILLEGAL

L HL L ×

Mode register H × × × ×

REF/SELF/MRS ILLEGAL

DESL

Nop → Enter idle after tRSC

accessing

L HHH×

NOP

Nop → Enter idle after tRSC

L HHL ×

BST

ILLEGAL

L HL H×

READ/READA ILLEGAL

LLLL×

ACT/PRE/PLL/ ILLEGAL

REF/SELF/MRS

Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data

BA: Bank Address, CA: Column Address, RA: Row Address

Notes

8

3

3

3, 8

3

3

Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.

2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down

mode.

3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),

depending on the state of that bank.

4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode.

All input buffers except CKE will be disabled.

5. Illegal if tRCD is not satisfied.

6. Illegal if tRAS is not satisfied.

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus trun around, and/or write recovery requirements.

9. Must mask preceding data which don’t satisfy tDPL.

10. Illegal if tRRD is not satisfied.

Data Sheet E0305E30 (Ver. 3.0)

19

Share Link: