EDS1232AATA-75MI View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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EDS1232AATA-75MI

128M bits SDRAM WTR (Wide Temperature Range)

Elpida Memory, Inc 

EDS1232AATA-MI

Read command to Write command interval

1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same

bank as the preceding read command, the write command can be performed after an interval of no less than 1

clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.

CLK

Command

CL=2

DQM

CL=3

E DQ (input)

DQ (output)

O CLK

LCommand

READ WRIT

in B0 in B1 in B2 in B3

High-Z

READ to WRITE Command Interval (1)

READ

WRIT

BL = 4

Burst write

DQM

CL=2

DQ

CL=3

2 clock

out out out in in in in

out out in in in in

PREAD to WRITE Command Interval (2)

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be

executed; it is necessary to separate the two commands with a precharge command and a bank active

r command.

3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1

cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the

oduct output buffer becomes High-Z before data input.

Data Sheet E0340E30 (Ver. 3.0)

34

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