CY7C4425-35AI View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

View to exact match

CY7C4425-35AI

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Read Cycle Timing

RCLK

REN

tENS

EF

tCLKH

tENH

tREF

tA

tCLK

tCLKL

NO OPERATION

Q0 –Q17

OE

WCLK

tOLZ

tOE

tSKEW2[14]

CY7C4425/4205/4215

CY7C4225/4235/4245

tREF

VALID DATA

tOHZ

WEN

Reset Timing[15]

42X5–7

tRS

RS

tRSR

REN, WEN,

LD

tRSF

EF,PAE

FF,PAF,

HF

Q0 - Q17

tRSF

tRSF

OE=1[16]

OE=0

42X5–8

Notes:

14. .tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the

rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.

15. The clocks (RCLK, WCLK) can be free-running during reset.

16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

7

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