CY7C135-15(2004) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

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CY7C135-15
(Rev.:2004)

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

Cypress Semiconductor 

CY7C135

CY7C1342

Architecture

The CY7C135 consists of an array of 4K words of 8 bits each

of dual-port RAM cells, I/O and address lines, and control sig-

nals (CE, OE, R/W). Two semaphore control pins exist for the

CY7C1342 (SEML/R).

Functional Description

Write Operation

Data must be set up for a duration of tSD before the rising edge

of R/W in order to guarantee a valid write. Since there is no

on-chip arbitration, the user must be sure that a specific loca-

tion will not be accessed simultaneously by both ports or erro-

neous data could result. A write operation is controlled by ei-

ther the OE pin (see Write Cycle No. 1 timing diagram) or the

R/W pin (see Write Cycle No. 2 timing diagram). Data can be

written tHZOE after the OE is deasserted or tHZWE after the

falling edge of R/W. Required inputs for write operations are

summarized in Table 1.

If a location is being written to by one port and the opposite

port attempts to read the same location, a port-to-port

flowthrough delay is met before the data is valid on the output.

Data will be valid on the port wishing to read the location tDDD

after the data is presented on the writing port.

Read Operation

When reading the device, the user must assert both the OE

and CE pins. Data will be available tACE after CE or tDOE after

OE are asserted. If the user of the CY7C1342 wishes to ac-

cess a semaphore, the SEM pin must be asserted instead of

the CE pin. Required inputs for read operations are summa-

rized in Table 1.

Semaphore Operation

The CY7C1342 provides eight semaphore latches which are

separate from the dual port memory locations. Semaphores

are used to reserve resources which are shared between the

two ports. The state of the semaphore indicates that a re-

source is in use. For example, if the left port wants to request

a given resource, it sets a latch by writing a zero to a sema-

phore location. The left port then verifies its success in setting

the latch by reading it. After writing to the semaphore, SEM or

OE must be deasserted for tSOP before attempting to read the

semaphore. The semaphore value will be available tSWRD +

tDOE after the rising edge of the semaphore write. If the left port

was successful (reads a zero), it assumes control over the

shared resource, otherwise (reads a one) it assumes the right

port has control and continues to poll the semaphore. When

the right side has relinquished control of the semaphore (by

writing a one), the left side will succeed in gaining control of

the semaphore. If the left side no longer requires the sema-

phore, a one is written to cancel its request.

Semaphores are accessed by asserting SEM LOW. The SEM

pin functions as a chip enable for the semaphore latches. CE

must remain HIGH during SEM LOW. A0–2 represents the

semaphore address. OE and R/W are used in the same man-

ner as a normal memory access. When writing or reading a

semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O0 is used. If a 0 is

written to the left port of an unused semaphore, a one will

appear at the same semaphore address on the right port. That

semaphore can now only be modified by the side showing a

Document #: 38-06038 Rev. *B

zero (the left port in this case). If the left port now relinquishes

control by writing a one to the semaphore, the semaphore will

be set to one for both sides. However, if the right port had

requested the semaphore (written a zero) while the left port

had control, the right port would immediately own the sema-

phore. Table 2 shows sample semaphore operations.

When reading a semaphore, all eight data lines output the

semaphore value. The read value is latched in an output reg-

ister to prevent the semaphore from changing state during a

write from the other port. If both ports request a semaphore

control by writing a 0 to a semaphore within tSPS of each other,

it is guaranteed that only one side will gain access to the sema-

phore.

Initialization of the semaphore is not automatic and must be

reset during initialization program at power-up. All sema-

phores on both sides should have a one written into them at

initialization from both sides to assure that they will be free

when needed.

Table 1. Non-Contending Read/Write

Inputs

Outputs

CE R/W OE SEM I/O0 – I/O7

Operation

H X X H High Z

Power-Down

HH L

L Data Out Read

Semaphore

X X H X High Z

I/O Lines Disabled

H L X L Data In

Write to Semaphore

L H L H Data Out Read

L L X H Data In

Write

LXX L

Illegal Condition

Table 2. Semaphore Operation Example

Function

No Action

Left port writes

semaphore

Right port writes 0 to

semaphore

Left port writes 1 to

semaphore

Left port writes 0 to

semaphore

Right port writes 1 to

semaphore

Left port writes 1 to

semaphore

Right port writes 0 to

semaphore

Right port writes 1 to

semaphore

Left port writes 0 to

semaphore

Left port writes 1 to

semaphore

I/O0-7

Left

1

0

0

1

1

0

1

1

1

0

1

I/O0-7

Right

1

1

1

0

0

1

1

0

1

1

1

Status

Semaphore free

Left port obtains

semaphore

Right side is denied

access

Right port is granted

access to Sema-

phore

No change. Left port

is denied access

Left port obtains

semaphore

No port accessing

semaphore address

Right port obtains

semaphore

No port accessing

semaphore

Left port obtains

semaphore

No port accessing

semaphore

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