CS5165GDWR16 View Datasheet(PDF) - Cherry semiconductor
Part Name
Description
View to exact match
CS5165GDWR16
Cherry semiconductor
CS5165GDWR16 Datasheet PDF : 19 Pages
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Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 14V;
2.8V DAC Code (VID4=VID2=VID1=VID0=1, VID3= 0), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s VCC Supply Current
Operating
Sleep Mode
1V < VFB < VDAC (max on-time)
No Loads on Gate(H) and Gate(L)
ENABLE = 0V
12
20
mA
300
600
µA
s VCC Monitor
Start Threshold
Stop Threshold
Hysteresis
GATE(H) Switching
GATE(H) not switching
Start - Stop
3.75
3.95
4.15
V
3.65
3.87
4.05
V
80
mV
s Error Amplifier
VFB Bias Current
VFB = 0V
0.1
COMP Source Current
COMP = 1.2V to 3.6V; VFB = 2.7V
15
30
COMP CLAMP Voltage
VFB = 2.7V, Adjust COMP voltage for 0.85
1.0
Comp current = 50µA
COMP Clamp Current
COMP = 0V
0.4
1.0
COMP Sink Current
Open Loop Gain
VCOMP =1.2V; VFB = 3V; VSS > 2.5V
180
400
Note 1
50
60
Unity Gain Bandwidth
Note 1
0.5
2
PSRR @ 1kHZ
Note 1
60
85
1.0
µA
60
µA
1.15
V
1.6
mA
800
µA
dB
MHz
dB
s GATE(H) and GATE(L)
High Voltage at 100mA
Low Voltage at 100mA
Measure VCC-GATE
Measure GATE
1.2
2.0
V
1.0
1.5
V
Rise Time
1.6V < GATE < (VCC- 2.5V)
40
80
ns
Fall Time
(VCC - 2.5V) > GATE > 1.6V
40
80
ns
GATE(H) to GATE(L) Delay GATE(H) < 2V, GATE(L) > 2V
30
65
100
ns
GATE(L) to GATE(H) Delay GATE(L) < 2V, GATE(H) > 2V
30
65
100
ns
GATE pull-down
Resistance to PGnd (note 1)
20
50
115
kΩ
s Fault Protection
SS Charge Time
SS Pulse Period
SS Duty Cycle
VFB = 0V
VFB = 0V
(Charge Time/Period) × 100
1.6
3.3
5.0
ms
25
100
200
ms
1.0
3.3
6.0
%
SS Comp Clamp Voltage
VFB Low Comparator
VFB = 2.7V, VSS = 0V
Increase VFB till no SS
pulsing and normal Off-time.
0.50
0.95
0.9
1.0
1.10
V
1.1
V
s PWM Comparator
Transient Response
VFB = 1.2 to 5V 500ns after
GATE(H) (after Blanking time) to
100
150
ns
GATE(H) = (VCC - 1V) to 1V
3
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