HMS39C7092 View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

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HMS39C7092

Embedded Flash MCU

Hynix Semiconductor 

Flash MCU(HMS39C7092)

Tables

Table 1.1 Pin Descriptions ......................................................................................... 16

Table 1.1 Pin Descriptions (Continued) ....................................................................... 17

Table 1.1 Pin Descriptions (Continued) ....................................................................... 18

Table 1.1 Pin Descriptions (Continued) ....................................................................... 19

Table 1.1 Pin Descriptions (Continued) ....................................................................... 20

Table 1.2 HMS39C7092 Operation modes .................................................................. 21

Table 1.3 Pin assignment by mode............................................................................. 22

Table 1.3 Pin assignment by mode (continued) ........................................................... 23

Table 1.3 Pin assignment by mode (continued) ........................................................... 24

Table 2.1 The ARM Instruction set .............................................................................. 31

Table 2.2 THUMB instruction set opcodes ................................................................... 34

Table 2.3 Condition code summary ............................................................................. 36

Table 2.4 PSR mode bit values .................................................................................. 38

Table 3.1 Bus Controller Pins ..................................................................................... 49

Table 3.2 BUS Controller Register Map....................................................................... 50

Table 3.3 Byte Lane condition by XA[0] ....................................................................... 55

Table 4.1 Pin Function Descriptions ............................................................................ 66

Table 4.2 Memory map of the MCU Controller ............................................................. 67

Table 4.3 MCU Controller Initial values in each mode .................................................. 67

Table 5.1 Register Map of the PMU ............................................................................ 77

Table 6.1 Interrupt Controller Default Setting Value...................................................... 85

Table 6.2 Memory Map of the Interrupt Controller ........................................................ 87

Table 6.3 Interrupt Source Trigger Mode..................................................................... 88

Table 7.1 Memory Map of the Watchdog Timer APB Peripheral .................................... 96

Table 7.2 Internal Counter Clock Sources (SYSCLK = 40 MHz).................................... 98

Table 8.1 Timer Global Control Register Map ............................................................ 108

Table 8.2 Timer Channel Control Register Map ......................................................... 108

Table 8.3 Timer Channel Starting Address ................................................................ 108

Table 9.1 Signal Descriptions ................................................................................... 127

Table 9.2 UART Register Address Map (0x1500 in UART1) ....................................... 129

Table 9.3 UART Register Reset Values ..................................................................... 129

Table 9.4a Divisor Values for each Baud rate (CLK=1.8432MHz)................................ 133

Table 9.4b Divisor Values for each Baud rate (CLK=3.6864MHz)................................ 133

Table 9.5 Interrupt Control Functions ........................................................................ 138

Table 9.6 Summary of Registers............................................................................... 142

Table 10.1 GPIO Register Memory Map.................................................................... 145

Table 12.1 Operating mode...................................................................................... 153

Table 12.2 Signal description of Figure 12.1(BUS Interface) ....................................... 155

Table 12.3 Flash Memory Registers.......................................................................... 156

Table 12.4 Control Register...................................................................................... 158

Table 12.5 Erase Block Register............................................................................... 159

Table 12.6 Status & Power Register ......................................................................... 160

Table 12.7 FR_SEL Value for access to internal Register ........................................... 173

Table 12.8 Setting for Register read/write.................................................................. 173

Table 12.9 Erase Block Register............................................................................... 174

Table 12.10 Setting for Flash PROM read/write ......................................................... 175

Preliminary

9

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