HMS39C7092 View Datasheet(PDF) - Hynix Semiconductor

Part Name

Description

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HMS39C7092

Embedded Flash MCU

Hynix Semiconductor 

Flash MCU(HMS39C7092)

Figure 8.2 Free-Running Counter Operation ............................................................. 115

Figure 8.3 Periodic Counter Operation...................................................................... 116

Figure 8.4 Example of 0 Output/1 Output .................................................................. 117

Figure 8.5 Example of Toggle Output ........................................................................ 118

Figure 8.6 Compare Match Signal Output Timing ...................................................... 118

Figure 8.7 Input Capture Operation .......................................................................... 119

Figure 8.8 Synchronized Operation Example ............................................................ 120

Figure 8.9 PWM Mode Operation Example 1 ............................................................ 121

Figure 8.10 PWM Mode Operation Example 2........................................................... 122

Figure 8.11 Reset-Synchronized PWM Mode Operation Example............................... 123

Figure 9.1 TOP BLOCK Diagram ............................................................................. 126

Figure 9.2 Internal UART Diagram ........................................................................... 128

Figure 10.1 GPIO Block Diagram and PADS Connections(example for Port A and Port B)

......................................................................................................................... 144

Figure 12.1 Block Diagram of Flash Memory ............................................................. 154

Figure 12.2 System Configuration When Using On-Board Boot Mode ......................... 161

Figure 12.3 Boot Mode Execution Procedure ............................................................ 162

Figure 12.4 User Mode Execution Procedure............................................................ 164

Figure 12.5 Flash Program & Program Verify Sequence............................................ 167

Figure 12.6 Flash Pre-program & Pre-program Verify Sequence ................................ 169

Figure 12.7 Flash Erase & Erase Verify Sequence .................................................... 171

Figure 12.8 Flash Erase Algorithm ........................................................................... 172

Figure 12.9 Timing Diagram of Read ........................................................................ 175

Figure 12.10 Timing Diagram of Pre-Program/Program ............................................. 176

Figure 12.11 Timing Diagram of Erase...................................................................... 176

Figure 12.12 Timing Diagram of Pre-Program/Program Verify .................................... 177

Figure 12.13 Timing Diagram of Erase Verify ............................................................ 177

Figure 13.1 Block Diagram of A/D Converter............................................................. 180

Figure 13.2 A/D converter Operation ........................................................................ 185

Figure 13.3 Example of Analog Input Circuit ............................................................. 188

Figure 13.4 A/D Converter Accuracy Definitions (1)................................................... 188

Figure 13.5 A/D Converter Accuracy Definitions (2)................................................... 189

Figure 14.1 The settling time of the crystal oscillator.................................................. 197

Figure 14.2 Reset Input Timing ................................................................................ 197

Figure 14.3 The Write Timing Diagram of the Bus Controller ...................................... 198

Figure 14.4 The Read Timing Diagram of the Bus Controller ...................................... 198

Figure 14.5 Basic Bus Cycle with External Wait State................................................ 199

Figure 14.6 Bus Release Mode Timing ..................................................................... 199

8

Preliminary

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