ATMEGA169PA-MCUR View Datasheet(PDF) - Atmel Corporation
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Description
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ATMEGA169PA-MCUR Datasheet PDF : 387 Pages
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ATmega169PA
7.6.4
7.6.5
7.6.6
the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be written to one to write the value into the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-
erwise no EEPROM write takes place.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
GPIOR2 – General Purpose I/O Register 2
Bit
0x2B (0x4B)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
GPIOR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
GPIOR1 – General Purpose I/O Register 1
Bit
0x2A (0x4A)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
GPIOR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
GPIOR0 – General Purpose I/O Register 0
Bit
0x1E (0x3E)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
GPIOR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
28
8171B–AVR–03/10
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