ADN2816 View Datasheet(PDF) - Analog Devices
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ADN2816 Datasheet PDF : 24 Pages
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Data Sheet
ADN2816
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
LVDS OUTPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Output Voltage High
Output Voltage Low
Differential Output Swing
Output Offset Voltage
Output Impedance
LVDS Outputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
I2C INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time Between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Conditions
VOH (see Figure 3), 655 Mb/s
VOL (see Figure 3), 655 Mb/s
VOD (see Figure 3), 655 Mb/s
VOS (see Figure 3)
Differential
20% to 80%
80% to 20%
TS (see Figure 2), OC-12
TH (see Figure 2), OC-12
LVCMOS
VIH
VIL
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
See Figure 10
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
TR/TF
tSU;STO
tBUF
Optional lock to REFCLK mode
@ REFCLKP or REFCLKN
VIL
VIH
VIH
VIL
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
VOH, IOH = −2.0 mA
VOL, IOL = 2.0 mA
1 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.
Min
Typ Max
Unit
925
250
1125
1475
mV
mV
320 400
mV
1200 1275
mV
100
Ω
115 220
ps
115 220
ps
760
800 840
ps
760
800 840
ps
0.7 VCC
−10.0
V
0.3 VCC V
+10.0 µA
0.4
V
600
1300
600
600
100
300
20 + 0.1 Cb1
600
1300
400
kHz
ns
ns
ns
ns
ns
ns
300
ns
ns
ns
0
V
VCC
V
100
mV p-p
10
160
MHz
100
ppm
2.0
V
0.8
V
5
µA
−5
µA
2.4
V
0.4
V
Rev. C | Page 5 of 24
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