AD73460(Rev0) View Datasheet(PDF) - Analog Devices
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AD73460 Datasheet PDF : 32 Pages
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AD73460
In Cascade Mode, both devices must know the number of devices
in the cascade to be able to output data at the correct time.
Control Register A contains a 3-bit field (DC0–2) that is pro-
grammed by the DSP during the programming phase. The
default condition is that the field contains 000b, which is equiva-
lent to a single device in cascade (see Table XVI). However, for
cascade operation this field must contain a binary value that is
one less than the number of devices in the cascade. With a cascade,
each device takes a turn to send an ADC result to the DSP. For
example, in a cascade of two devices the data will be output as
Device 2-Channel 1, Device 1-Channel 1, Device 2-Channel 2,
Device 1-Channel 2 etc. When the first device in the cascade
has transmitted its channel data there is an additional SCLK
period during which the last device asserts its SDOFS as it
begins its transmission of the next channel. This will not cause
a problem for most DSPs as they count clock edges after a
frame sync and hence the extra bit will be ignored.
When two devices are connected in cascade there are also
restrictions concerning which ADC channels can be powered
up. In all cases the cascaded devices must all have the same
channels powered up (i.e., for a cascade requiring Channels 1
and 2 on Device 1 and Channel 5 on Device 2, Channels 1, 2,
and 5 must be powered up on both devices to ensure correct
operation).
Table XVI. Device Count Settings
DC2
0
0
0
0
1
1
1
1
DC1
0
0
1
1
0
0
1
1
DC0
0
1
0
1
0
1
0
1
Cascade Length
1
2
3
4
5
6
7
8
FUNCTIONAL DESCRIPTION—DSP
The AD73460 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc-
tions. Every instruction can be executed in a single processor cycle.
The AD73460 assembly language uses an algebraic syntax for ease
of coding and readability. A comprehensive set of development
tools supports program development.
Figure 10 is an overall block diagram of the AD73460. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC), and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi-
tives are also supported. The MAC performs single-cycle
multiply, multiply/add, and multiply/subtract operations with 40
bits of accumulation. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these com-
putational units. The sequencer supports conditional jumps,
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73460 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
AD73460
MEMORY
16K PM 16K DM
(OPTIONAL (OPTIONAL
8K)
8K)
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
ADSP-2100 BASE
ARCHITECTURE
REF
SERIAL PORT
SPORT 2
ADC1 ADC2 ADC3 ADC4 ADC5 ADC6
ANALOG FRONT END
SECTION
Figure 10. Functional Block Diagram
–20–
REV. 0
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