AD5821 View Datasheet(PDF) - Analog Devices
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AD5821 Datasheet PDF : 16 Pages
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AD5821
AC SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted.
Table 2.
Parameter
Output Current Settling Time
Slew Rate
Major Code Change Glitch Impulse
Digital Feedthrough3
B Version1, 2
Min Typ Max
250
0.3
0.15
0.06
Unit
μs
mA/μs
nA-s
nA-s
1 Temperature range is as follows: B Version = −40°C to +85°C.
2 Guaranteed by design and characterization; not production tested.
3 See the Terminology section.
Test Conditions/Comments
VDD = 3.6 V, RL = 25 Ω, LL = 680 μH, ¼ scale to ¾ scale change (0x100 to 0x300)
1 LSB change around major carry
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
fSCL
t1
t2
t3
t4
t5
t6 2
t7
t8
t9
t10
t11
CB
B Version
Limit at TMIN, TMAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
300
20 + 0.1 CB3
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of both SCL and SDA when receiving
May be CMOS driven
tF, fall time of SDA when receiving
tF, fall time of both SCL and SDA when transmitting
Capacitive load for each bus line
1 Guaranteed by design and characterization; not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VINH MIN of the SCL signal) to bridge the undefined region of the SCL falling edge.
3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
Timing Diagram
SDA
t9
t3
t10
t11
t4
SCL
t4
START
CONDITION
t6
t2
t5
t7
t1
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
t8
STOP
CONDITION
Rev. 0 | Page 4 of 16
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