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AD5821 View Datasheet(PDF) - Analog Devices

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AD5821 Datasheet PDF : 16 Pages
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AD5821
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications TMIN to TMAX,
unless otherwise noted.
Table 1.
Parameter
DC PERFORMANCE
Resolution
Relative Accuracy2
Differential Nonlinearity2, 3
Zero-Code Error2, 4
Offset Error @ Code 162
Gain Error2
Offset Error Drift4, 5
Gain Error Drift2, 5
B Version1
Min
Typ Max
10
±1.5 ±4
±1
0
15
0.5
±0.6
10
±0.2 ±0.5
Unit
Bits
LSB
LSB
mA
mA
% of FSR
μA/°C
LSB/°C
Test Conditions/Comments
VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V
with reduced performance
117 μA/LSB
Guaranteed monotonic over all codes
All 0s loaded to DAC
@ 25°C
OUTPUT CHARACTERISTICS
Minimum Sink Current4
3
mA
Maximum Sink Current
120
mA
Output Current During XSHUTDOWN
80
nA
XSHUTDOWN = 0
Output Compliance5
0.6
VDD
V
Output voltage range over which maximum 120 mA
sink current is available
Output Compliance5
0.48
VDD
V
Output voltage range over which 90 mA sink current
is available
Power-Up Time
20
μs
To 10% of FS, coming out of power-down mode; VDD = 5 V
LOGIC INPUTS (XSHUTDOWN)5
Input Current
±1
μA
Input Low Voltage, VINL
0.54
V
VDD = 2.7 V to 5.5 V
Input High Voltage, VINH
1.3
V
VDD = 2.7 V to 5.5 V
Pin Capacitance
3
pF
LOGIC INPUTS (SCL, SDA)5
Input Low Voltage, VINL
−0.3
+0.54 V
VDD = 2.7 V to 3.6 V
Input High Voltage, VINH
1.26
VDD + 0.3 V
VDD = 2.7 V to 3.6 V
Input Low Voltage, VINL
−0.3
+0.54 V
VDD = 3.6 V to 5.5 V
Input High Voltage, VINH
1.4
VDD + 0.3 V
VDD = 3.6 V to 5.5 V
Input Leakage Current, IIN
±1
μA
VIN = 0 V to VDD
Input Hysteresis, VHYST
0.05 VDD
V
Digital Input Capacitance, CIN
Glitch Rejection6
6
pF
50
ns
Pulse width of spike suppressed
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)
IDD specification is valid for all DAC codes
VDD = 2.7 V to 3.6 V
IDD (Power-Down Mode)7
2.5 4
0.5
mA
VINH = 1.8 V, VINL = GND, VDD = 3.6 V
μA
VINH = 1.8 V, VINL = GND
1 Temperature range is as follows: B Version = −30°C to +85°C.
2 See the Terminology section.
3 Linearity is tested using a reduced code range: Code 32 to Code 1023.
4 To achieve near zero output current, use the power-down feature.
5 Guaranteed by design and characterization; not production tested. XSHUTDOWN is active low. SDA and SCL pull-up resistors are tied to 1.8 V.
6 Input filtering on both the SCL and the SDA inputs suppresses noise spikes that are less than 50 ns.
7 XSHUTDOWN is active low.
Rev. 0 | Page 3 of 16

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