MT9T001 View Datasheet(PDF) - Micron Technology

Part Name

Description

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MT9T001

3-MEGAPIXEL DIGITAL IMAGE SENSOR

Micron Technology 

PRELIMINARY

MT9T001

3-MEGAPIXEL DIGITAL IMAGE SENSOR

Table 6: Register Descriptions (continued)

REGISTER BIT

Pixel Clock Control

0x0A

15

10:8

6:0

Frame Restart

0x0B

0

Shutter Delay

0x0C

10:0

Reset

0x0D

0

Read Mode 1

0x1E

8

9

10

11

Read Mode 2

0x20

0

9

10

DESCRIPTION

Invert Pixel Clock—default = 0x00 (0)

When set, line_valid, frame_valid, and data10_out will be set up to the rising edge of PIXCLK.

When clear, they are set up to the falling edge. This is accomplished by inverting the PIXCLK

output.

Shift Pixel Clock—default = 0x00 (0)

Two's compliment value representing how far to shift the PIXCLK output pin relative to DOUT,

in CLKIN cycles. Positive values shift PIXCLK later in time relative to DOUT (and thus relative to

the internal array/datapath clock. No effect unless PIXCLK is divided by Divide Pixel Clock.

Divide Pixel Clock —default = 0x00 (0)

Produces a PIXCLK that is divided by the value times two. The value must be a power of 2. This

will slow down the internal clock in the array control and datapath blocks, including pixel

readout. It will not affect the two-wire serial interface clock. A value of 0 corresponds to a

PIXCLK with the same frequency as CLK_IN. A value of 1 means f_PIXCLK = (f_CLK_IN / 2); 2

means f_PIXCLK = (f_CLK_IN / 4); 64 means f_PIXCLK = (f_CLK_IN / 128); etc.

Setting bit 0 to “1” of Reg0x0B will cause the sensor to abandon the readout of the current

frame and restart from the first row. This register automatically resets itself to 0x0000 after the

frame restart. The first frame after this event is considered to be a "bad frame" (see description

for Reg0x20, bit 0).

Shutter delay—default = 0x0000 (0). This is the number of pixel clocks that the timing and

control logic waits before asserting the reset for a given row.

Setting this bit will put the sensor into reset mode, which will set the sensor to its default

power-up state. Clearing this bit will resume normal operation.

Snapshot Mode—default is 0 (continuous mode).

1 = enable Snapshot trigger signal can come from outside signal (trigger pin 8 on the sensor) or

from serial interface register restart, i.e. programming a “1” to bit 0 of Reg0x0B.

Strobe Enable—default is 0 (no strobe signal).

1 = enable strobe (signal output from the sensor during the time all rows are integrating). See

strobe width for more information.

Strobe Width—default is 0 (strobe signal width at minimum length, one row of integration

time, prior to Line_Valid going high).

1 = extend strobe width (strobe signal width extends to entire time all rows are integrating;

shutter width must be >= row size + vertical blanking).

Strobe Override—default is 0 (strobe signal created by digital logic).

1 = override strobe signal (strobe signal is set high when this bit is set, low when this bit is set

low. It is assumed that strobe enable is set to “0” if strobe override is being used).

No bad frames—1 = output all frames (including bad frames).

0 = default, only output good frames. A bad frame is defined as the first frame following a

change to: window size or position, horizontal blanking, row or column skip, or mirroring.

1 = "Continuous" LINE_VALID (continue producing Line_Valid during vertical blanking).

0 = Normal Line_Valid (default, no Line_Valid during vertical blank).

1 = LINE_VALID = "Continuous" LINE_VALID XOR FRAME_VALID.

0 = LINE_VALID determined by bit 9 (default).

09005aef80c64010

MT9T001_3100_DS_2.fm - Rev. C 9/04 EN

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc. All rights reserved.

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