VV5409C001 View Datasheet(PDF) - Vision
Part Name
Description
View to exact match
VV5409C001 Datasheet PDF : 39 Pages
| |||
VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
Register
Index
Bit
Function
Default
Comment
2 Monitor window size set by
serial-interface
communication
Yes/No
3 Narrow Black Calibration
target window
Yes/No
7:4 used
0
Allow the serial-interface to set the
Black Calibration monitor window size
directly
0
By default the target window size for
the Black Calibration (calibration
phase) is set to the widest position
0
Table 6.26 : [112] - Black Level Monitor/Calibration Window Sizes
[117 - 118] - Control Registers 0 and 1- CR0 and CR1
Bit
Function
PAL/NTSC
value
Default
Comment
0 Enable bit line clamp
0
Off/On
1 New PXRDB scheme
0
Off/On
2 Inhibit horizontal shift register
0
Off/On
3 Enable anti-blooming
1
protection
Off/On
4 Inhibit OSA fast reset
0
Off/On
5 External bit line white
0
reference
Off/On
6 CDSH Mode
0
New/Old
7 VCDSH Voltage
1
3.0 / 3.9V
0
0
0
0
0
0
0
By asserting this control bit,
the falling edge of CDSH is
forced to occur earlier in the
line timing
0
0 - VCDSH = 3.0 V
1 - VCDSH = 3.9 V
Table 6.27 : [117] - Control Register CR0
PAL/NTSC
Bit
Function
value
Default
Comment
0 Stand-by
Off/On
cd38041a.fm
0
0
Powers down ALL analogue
circuitry
Table 6.28 : [118] - Control Register CR1
Commercial In Confidence
08/10/98
55
VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
PAL/NTSC
Bit
Function
value
Default
Comment
1 Power Down - ADC
0
Off/On
2 Power Down - ADC Top
0
Reference
Off/On
3 Power Down - AVO Output Buffer
0
Off/On
4 B1 Offset DAC Gain Select
1
Low (x1) / High (x2)
5 Inhibit Quiet ADC Signal
0
Off / On
7:6 RST/MRST Phase Delay Setting
01
0° / 90° / 180° / 270°
0
0
0
0
0
00
00: Phase Delay = 0° (Default)
01: Phase Delay = 90°
10: Phase Delay = 180°
11: Phase Delay = 270°
Table 6.28 : [118] - Control Register CR1
Notes:
1. The signal enabling the external ADC functionality, is the logical OR of CR0 [0] bit and the invert of the
ADCVDD pin
2. The low-power select signal for the analogue circuitry, is the logical OR of PD0 [0] and Setup0 [0].
[119] - ADC Setup Register AS0
Bit
Function
Default
Comment
1:0 ADC Clock Fine Delay Setting
0 ns / 4 ns / 8 ns / 16 ns
3:2 ADC Clock Phase Delay Setting
0° / 90° / 180° / 270°
5:4 PCK Clock Fine Delay Setting
0 ns / 4 ns / 8 ns / 16 ns
6 ADC Clock Generator Setting
Fast / Slow
7 Unused
00
00: Clock Delay = 0 ns (Default)
01: Clock Delay = 4 ns
10: Clock Delay = 8 ns
11: Clock Delay = 16 ns
01
00: Phase Delay = 0°
01: Phase Delay = 90° (Default)
10: Phase Delay = 180°
11: Phase Delay = 270°
00
00: Clock Delay = 0 ns (Default)
01: Clock Delay = 4 ns
10: Clock Delay = 8 ns
11: Clock Delay = 16 ns
1
1 - CIF Mode
0 - CCIR-601/656. NTSC, PAL modes
Table 6.29 : [119] - ADC Setup Register AS0
Commercial In Confidence
cd38041a.fm
08/10/98
56
Share Link: 