VV6850 View Datasheet(PDF) - Vision

Part Name

Description

View to exact match

VV6850

High resolution CMOS Image Sensor with support for external FPN cancellation and serial interface control, available in colour (6850) and monochrome (5850) versions

Vision 

Sensor Architecture

Reset and Read Vertical Shift Registers

The resetting and reading of pixels is performed on a line by line basis, that is a row of column

amplifiers reads a whole line of pixel voltages in parallel. The reset/integrate/read cycle for a line

of pixels is controlled by the Reset Vertical and Read Vertical shift registers (VSRs).

The length of the ‘Frame Integrate’ pulse, FI, propagating along the Reset Vertical shift register

sets the pixel integration time. FI going high at a point along the VSR releases that line of pixels

from RESET, starting the integration period. The two-line ‘Frame Read’ pulse, FR, which comes

at the end of the integrate period, starts the field readout, which proceeds from ‘bottom’ to ‘top’.

As FR propagates along the Read Vertical shift register, it controls which line is to be read. For

exposure control by means of a shutter mechanism, FI should be held high throughout the frame

y integrate/read cycle.

The Vertical Shift Registers are clocked by the Line Clock pulse, LCK. Within a frame, first an even

r line, then an odd line is read. This is controlled by the EVEN clock, which must be half the LCK

frequency and change two PCKs before LS (Line Start) rises. A pair of lines may be ‘skipped over’

(for example as in ‘Cine’ mode—see: HORIZONTAL SHIFT REGISTER), by inserting two LCK pulses and

one EVEN pulse between line readout sequences. .

a

LCK

EVEN

FI

in

FR

AVO

Exposure

l i AVO Not Valid

m

1014 Lines

Black Ref Line

Valid Video Line

Note: If FR does not rise with the rising edge of EVEN, that is if EVEN is high during the second

e line period of the FR pulse, the AVO-valid line readout sequence is offset by one line.

r Further control of the VSRs is effected by: VCLRB (Clear Reset and Read); VSETB (preset Reset

to ones); CDSR (reset row, but do not advance VSRs). The PXRD input to the Read VSR enables

P a line of pixels to be read out. (See: OPERATING MODES for more details.)

The first six lines in the array are black reference lines. The reset/integrate cycle for these lines is

controlled by a third shift register, defined by bits CR[4] and CR[3] in the Control Register (see:

CONTROL REGISTER/SERIAL DATA INTERFACE). This shift register can either hold the black reference

lines in permanent reset, allow minimum exposure or have the same integration time (exposure)

as the rest of the array.

The readout sequence, initiated by FR going high, is therefore: six black lines followed by eight

colour characterisation lines, 992 valid video lines and another eight colour characterisation lines.

For Cine this becomes: four black lines, four colour characterisation, 496 valid video lines and four

colour characterisation lines

16/06/97

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